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1. 发明授权

US08005130B2 Transmitter and receiver using forward clock overlaying link information 有权
标题翻译：发射机和接收机使用正向时钟叠加链路信息
公开(公告)号：US08005130B2
公开(公告)日：2011-08-23
申请号：US11826300
申请日：2007-07-13
申请人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
发明人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
IPC分类号： H04B1/38
CPC分类号： H04L7/0337
摘要： A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
摘要翻译：一种在保持通信质量的同时减少数据信号线上的负载的发送和接收技术，从而可以提高数据信道的吞吐量。在收发机中，发射机侧具有将通过对链路信息进行编码而获得的比特序列发送到时钟信号线的编码器电路，并且接收机侧具有时钟和数据恢复电路17，时钟和数据恢复电路17从从时钟信号线，对所提取的信号进行解码以再现链接信息的解码器电路19以及基于时钟分量来调整低于1比特的歪斜的位歪斜电路21。

2. 发明申请

US20080056336A1 Transmitter and receiver using forward clock overlaying link information 有权
标题翻译：发射机和接收机使用正向时钟叠加链路信息
公开(公告)号：US20080056336A1
公开(公告)日：2008-03-06
申请号：US11826300
申请日：2007-07-13
申请人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
发明人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
IPC分类号： H04B1/38
CPC分类号： H04L7/0337
摘要： A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
摘要翻译：一种在保持通信质量的同时减少数据信号线上的负载的发送和接收技术，从而可以提高数据信道的吞吐量。在收发机中，发射机侧具有将通过对链路信息进行编码而获得的比特序列发送到时钟信号线的编码器电路，并且接收机侧具有时钟和数据恢复电路17，时钟和数据恢复电路17从从时钟信号线，对所提取的信号进行解码以再现链接信息的解码器电路19以及基于时钟分量来调整低于1比特的歪斜的位歪斜电路21。

3. 发明授权

US08445832B2 Optical communication device 有权
标题翻译：光通信设备
公开(公告)号：US08445832B2
公开(公告)日：2013-05-21
申请号：US13201212
申请日：2009-03-05
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F3/08 , H01J43/00 , H01J40/14 , G01R19/00
CPC分类号： H03F3/087 , H03F1/223 , H03F1/34 , H03F3/082 , H03F3/3022 , H03F3/505 , H03F2200/453 , H04B10/6933
摘要： An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
摘要翻译：提供可以高速运转的光通信装置。例如，光通信装置包括：前置放大器电路PREAMP1，放大来自光电二极管PD的电流信号Iin，将放大后的信号变换为电压信号; 以及控制PREAMP1的操作的操作点控制器电路VTCTL1。 PREAMP1包括由反馈电阻Rf1形成的负反馈路径，并且包括：根据工作点控制信号Vcon的电平移位电路LS1电平移位; 以及连接到LS1的后级并且以高增益进行放大操作的放大器电路AMP1。 VTCTL1包括由与AMP1相同的电路和电路参数配置的电路复用电路，并且电连接在输入和输出端之间，并产生Vcon，使得该复制电路的输出直流电平与输入直流电平相匹配的AMP1。

4. 发明授权

US07714644B2 Amplifier circuit 失效
标题翻译：放大器电路
公开(公告)号：US07714644B2
公开(公告)日：2010-05-11
申请号：US12166666
申请日：2008-07-02
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F1/26 , H03F1/34 , H03F3/45085 , H03F3/45183 , H03F3/45968 , H03F2200/372 , H03F2200/375 , H03F2203/45534
摘要： An amplifier circuit block and a compensation circuit block are provided. The amplifier circuit block includes an analog adder for subtracting an output signal of the compensation circuit block from an input signal and an amplifier circuit operating in a wide band. The compensation circuit block includes an amplifier circuit with a low offset voltage and a low noise in a low frequency region, an analog adder block for subtracting an output signal of the amplifier circuit from an output signal of the amplifier circuit and generating a differential signal thereof, and a feedback circuit block for negatively feeding back the differential signal to the analog adder. The amplifier circuit block can reduce the offset voltage and the low-band noise by the negative feedback of the differential signal, and at the same time, the operation band of the entire amplifier circuit can be decided by the characteristic of the amplifier circuit.
摘要翻译：提供放大器电路块和补偿电路块。放大器电路块包括用于从输入信号中减去补偿电路块的输出信号的模拟加法器和在宽带中工作的放大器电路。补偿电路块包括在低频区域具有低失调电压和低噪声的放大器电路，用于从放大器电路的输出信号中减去放大器电路的输出信号并产生其差分信号的模拟加法器块以及用于将差分信号负反馈给模拟加法器的反馈电路块。放大器电路块可以通过差分信号的负反馈来减小偏移电压和低带噪声，同时整个放大器电路的工作频带可以由放大器电路的特性决定。

5. 发明申请

US20110316632A1 OPTICAL COMMUNICATION DEVICE 有权
标题翻译：光通信设备
公开(公告)号：US20110316632A1
公开(公告)日：2011-12-29
申请号：US13201212
申请日：2009-03-05
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F3/16 , H03F1/22 , H03G3/20
CPC分类号： H03F3/087 , H03F1/223 , H03F1/34 , H03F3/082 , H03F3/3022 , H03F3/505 , H03F2200/453 , H04B10/6933
摘要： An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
摘要翻译：提供可以高速运转的光通信装置。例如，光通信装置包括：前置放大器电路PREAMP1，放大来自光电二极管PD的电流信号Iin，将放大后的信号变换为电压信号; 以及控制PREAMP1的操作的操作点控制器电路VTCTL1。 PREAMP1包括由反馈电阻Rf1形成的负反馈路径，并且包括：根据工作点控制信号Vcon的电平移位电路LS1电平移位; 以及连接到LS1的后级并且以高增益进行放大操作的放大器电路AMP1。 VTCTL1包括由与AMP1相同的电路和电路参数配置的电路复用电路，并且电连接在输入和输出端之间，并产生Vcon，使得该复制电路的输出直流电平与输入直流电平相匹配的AMP1。

6. 发明申请

US20090009240A1 Amplifier Circuit 失效
标题翻译：放大器电路
公开(公告)号：US20090009240A1
公开(公告)日：2009-01-08
申请号：US12166666
申请日：2008-07-02
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F1/36
CPC分类号： H03F3/45475 , H03F1/26 , H03F1/34 , H03F3/45085 , H03F3/45183 , H03F3/45968 , H03F2200/372 , H03F2200/375 , H03F2203/45534
摘要： An amplifier circuit block and a compensation circuit block are provided. The amplifier circuit block includes an analog adder for subtracting an output signal of the compensation circuit block from an input signal and an amplifier circuit operating in a wide band. The compensation circuit block includes an amplifier circuit with a low offset voltage and a low noise in a low frequency region, an analog adder block for subtracting an output signal of the amplifier circuit from an output signal of the amplifier circuit and generating a differential signal thereof, and a feedback circuit block for negatively feeding back the differential signal to the analog adder. The amplifier circuit block can reduce the offset voltage and the low-band noise by the negative feedback of the differential signal, and at the same time, the operation band of the entire amplifier circuit can be decided by the characteristic of the amplifier circuit.
摘要翻译：提供放大器电路块和补偿电路块。放大器电路块包括用于从输入信号中减去补偿电路块的输出信号的模拟加法器和在宽带中工作的放大器电路。补偿电路块包括在低频区域具有低失调电压和低噪声的放大器电路，用于从放大器电路的输出信号中减去放大器电路的输出信号并产生其差分信号的模拟加法器块以及用于将差分信号负反馈给模拟加法器的反馈电路块。放大器电路块可以通过差分信号的负反馈来减小偏移电压和低带噪声，同时整个放大器电路的工作频带可以由放大器电路的特性决定。

7. 发明授权

US07216269B2 Signal transmit-receive device, circuit, and loopback test method 失效
标题翻译：信号发射接收设备，电路和环回测试方法
公开(公告)号：US07216269B2
公开(公告)日：2007-05-08
申请号：US10309886
申请日：2002-12-05
申请人： Takashige Baba , Tatsuya Saito , Hiroki Yamashita , Yusuke Takeuchi , Satoru Isomura
发明人： Takashige Baba , Tatsuya Saito , Hiroki Yamashita , Yusuke Takeuchi , Satoru Isomura
IPC分类号： G01R31/28
CPC分类号： H04B10/035 , H04B10/071 , H04L1/243
摘要： A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a loopback test on a signal transmit-receive device. The loopback test circuit uses an error detecting circuit, a test signal producing circuit, and a wiring for transmitting error information. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern. The test signal producing circuit produces the test signal pattern based on error information. If an error is detected, the error signal is transmitted to the test signal producing circuit through the wiring. The test signal producing circuit produces a predetermined test signal pattern if the error signal DE has an L level; upon receiving H level, it sends back the predetermined test signal pattern to the first communication device.
摘要翻译：本发明的信号发送接收装置减少了连接发送电路组和接收电路组所需的高速信号线的数量，并且对信号发送接收装置进行环回测试。环回测试电路使用错误检测电路，测试信号产生电路和用于发送错误信息的布线。误差检测电路将预先由第一通信设备定义的测试信号模式与接收到的信号模式进行比较。测试信号产生电路基于错误信息产生测试信号模式。如果检测到错误，则误差信号通过布线传输到测试信号产生电路。如果误差信号DE具有L电平，则测试信号产生电路产生预定的测试信号模式; 在接收到H电平后，将预定的测试信号模式发送回第一通信设备。

8. 发明授权

US06330703B1 Method and circuit for determining the power consumption requirements for a semiconductor logic circuit and designing the circuit accordingly 失效
标题翻译：用于确定半导体逻辑电路的功耗要求并相应地设计电路的方法和电路
公开(公告)号：US06330703B1
公开(公告)日：2001-12-11
申请号：US09041121
申请日：1998-03-12
申请人： Tatsuya Saito , Masayoshi Yagyu , Hiroki Yamashita , Tsuneyo Chiba , Masakazu Yamamoto
发明人： Tatsuya Saito , Masayoshi Yagyu , Hiroki Yamashita , Tsuneyo Chiba , Masakazu Yamamoto
IPC分类号： G06F1750
CPC分类号： G01R31/3004 , G06F2217/78
摘要： A logic circuit determines the power consumption of a semiconductor integrated device by taking into consideration the variation of the rate of operation. A control signal (TEST) is applied to each control signal input port (Tin) of flip-flop circuits of flip-flop circuit groups and a logic gate circuit having a plurality of input ports A and B in a combined circuit group. If the control signal (TEST) is low, both the flip-flop circuits and the logic gate circuit operate normally. However, if the control signal (TEST) is high, each of them performs the power consumption test. Regardless of the value of input signals applied to input ports D1 and D2 of the flip-flop circuits, the flip-flop circuits are controlled to have a repetitive output signal of high and low levels at ports Q1 and Q2, in synchronism with a clock signal. Through this operation test, operational failure is reduced and the quality of semiconductor chip production is guaranteed, because it is possible to predict accurately the power consumption when designing the logic circuit due to the relationship between the rate of operation and the power consumption.
摘要翻译：逻辑电路通过考虑操作速率的变化来确定半导体集成器件的功耗。控制信号（TEST）被施加到组合电路组中具有多个输入端口A和B的触发器电路组的触发器电路的每个控制信号输入端口（Tin）和逻辑门电路。如果控制信号（TEST）低，触发器电路和逻辑门电路均正常工作。但是，如果控制信号（TEST）为高，则进行功耗测试。不管施加到触发器电路的输入端口D1和D2的输入信号的值如何，触发器电路被控制为具有在时钟Q1与Q2的端口Q1和Q2的高电平和低电平的重复输出信号信号。通过这种操作测试，可以降低运行故障，保证半导体芯片生产的质量，因为由于操作速率和功耗之间的关系，可以准确地预测设计逻辑电路时的功耗。

9. 发明授权

US06202168B1 Device for regulating variation of delay time for data transfer between logic circuits 失效
标题翻译：用于调节逻辑电路之间数据传输的延迟时间变化的装置
公开(公告)号：US06202168B1
公开(公告)日：2001-03-13
申请号：US09113332
申请日：1998-07-10
申请人： Tatsuya Saito , Tetsuya Umemura , Hiroki Yamashita
发明人： Tatsuya Saito , Tetsuya Umemura , Hiroki Yamashita
IPC分类号： G06F104
CPC分类号： H04L7/033 , G01R31/31908 , H04L7/0008 , H04L7/0041 , H04L7/04
摘要： The delay time for the transfer of data signals between pluralities of logic circuits is automatically regulated to be in a desired range. In order to regulate the delay time of the data signal transfer, a common standard signal SYNC is distributed to the logic circuits from a standard signal generator source. In the sending side of one logic circuit, the standard signal is applied through a selector circuit to a flip-flop circuit and then transferred to the receiving side of another logic circuit. Specifically, the transferred standard signal passes through a variable delay circuit to a flip flop circuit on the receiving side of the other logic circuit where it is compared with the standard signal received from the standard signal generator source, which has passed through a delay circuit of a standard delay value. The result of the comparison is used to adjust the variable delay circuit that controls the delay time for the transferred standard signal. Once the variable delay circuit is adjusted with the standard signal, the selector selects normal data signals for transfer between the logic circuits with the appropriate delay. The standard signal can also be used to synchronize the generation of test pattern signals generated in each of the logic circuits.
摘要翻译：在多个逻辑电路之间传送数据信号的延迟时间被自动调节到期望的范围内。为了调节数据信号传输的延迟时间，从标准信号发生器源将公共标准信号SYNC分配给逻辑电路。在一个逻辑电路的发送侧，通过选择器电路将标准信号施加到触发器电路，然后传送到另一逻辑电路的接收侧。具体地，传送的标准信号通过可变延迟电路到另一个逻辑电路的接收侧的触发电路，与从标准信号发生器源接收的标准信号进行比较，该标准信号已通过延迟电路标准延迟值。比较结果用于调整控制传输标准信号的延迟时间的可变延迟电路。一旦用标准信号调整可变延迟电路，选择器就选择正常的数据信号，以便在逻辑电路之间以适当的延迟进行传输。标准信号也可用于同步在每个逻辑电路中产生的测试图形信号的产生。

10. 发明授权

US06191647B1 Low noise integrated circuit device for reducing a noise on LSI power supply nets to supply electric charges required to operate IC 有权
标题翻译：低噪声集成电路器件，用于降低LSI电源网络上的噪声，以提供操作IC所需的电荷
公开(公告)号：US06191647B1
公开(公告)日：2001-02-20
申请号：US09220372
申请日：1998-12-24
申请人： Katsuya Tanaka , Masayoshi Yagyu , Tatsuya Saito , Tetsuya Uemura , Tomohisa Iwanaga , Hiroki Yamashita , Takeshi Kato
发明人： Katsuya Tanaka , Masayoshi Yagyu , Tatsuya Saito , Tetsuya Uemura , Tomohisa Iwanaga , Hiroki Yamashita , Takeshi Kato
IPC分类号： H03K500
CPC分类号： H03K19/00346
摘要： A condenser having a huge area is required to reduce a noise on LSI power supply nets (−&Dgr;VDD) of an integrated circuit because a bypass condenser can only utilize a part of accumulated electric charges. A noise of LSI power supply nets is suppressed by generating a noise of a reversed polarity (+&Dgr;VDD) to the noise on the LSI power supply nets (−&Dgr;VDD), based upon a noise reducing circuit discharging a condenser charged with a high voltage. A noise reduction effect equivalent to a bypass condenser having a large capacity is obtained even when a condenser having a small capacity is used.
摘要翻译：需要具有巨大面积的电容器来减小集成电路的LSI电源网（-DELTAVDD）上的噪声，因为旁路电容器只能使用一部分累积的电荷。基于降低放电高电压的电容器的噪声降低电路，对LSI电源网（-DELTAVDD）的噪声产生相反极性（+ DELTAVDD）的噪声来抑制LSI电源网的噪声。即使使用容量小的冷凝器，也能够获得与大容量的旁路电容器相当的噪声降低效果。

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