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1. 发明授权

US4219369A Method of making semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US4219369A
公开(公告)日：1980-08-26
申请号：US931007
申请日：1978-08-04
申请人： Katsumi Ogiue , Takahisa Nitta , Kazumichi Mitsusada , Masato Iwabuchi , Masanori Odaka
发明人： Katsumi Ogiue , Takahisa Nitta , Kazumichi Mitsusada , Masato Iwabuchi , Masanori Odaka
IPC分类号： H01L21/033 , H01L21/308 , H01L21/32 , H01L21/388 , H01L21/762 , H01L21/8222 , H01L21/26
CPC分类号： H01L21/388 , H01L21/033 , H01L21/308 , H01L21/32 , H01L21/7621 , H01L21/76216 , H01L21/76232 , H01L21/8222 , Y10S148/117 , Y10S148/143
摘要： The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.
摘要翻译：本发明涉及一种制造半导体集成电路器件的方法，其目的在于减小将相邻半导体元件彼此隔离的隔离区的尺寸。本发明的方法具有以下步骤：在衬底上形成不同导电类型的扩散杂质的沉积层与衬底的沉积层，在沉积层上形成具有孔的掩模膜，通过使用掩模膜进行蚀刻作为扩散掩模，以蚀刻沉积层和基板下面的部分，从而形成将沉积层分成岛状沉积层部分的凹槽，并且将每个岛状沉积层中的杂质拉伸和扩散沉积层部分以形成构成半导体元件的一部分的扩散层。

2. 发明授权

US4630095A Packaged semiconductor device structure including getter material for decreasing gas from a protective organic covering 失效
标题翻译：封装的半导体器件结构包括用于从保护性有机覆盖物中减少气体的吸气剂材料
公开(公告)号：US4630095A
公开(公告)日：1986-12-16
申请号：US626200
申请日：1984-06-29
申请人： Kanji Otsuka , Kunizou Sahara , Masao Sekibata , Kazumichi Mitsusada , Katsumi Ogiue
发明人： Kanji Otsuka , Kunizou Sahara , Masao Sekibata , Kazumichi Mitsusada , Katsumi Ogiue
IPC分类号： H01L23/02 , H01L23/057 , H01L23/26 , H01L23/31 , H01L23/556 , H01L23/10 , H01L23/04 , H01L23/16 , H01L23/30
CPC分类号： H01L23/26 , H01L23/057 , H01L23/3157 , H01L23/3171 , H01L23/556 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/8592 , H01L24/45 , H01L24/48 , H01L2924/0102 , H01L2924/01039 , H01L2924/01046 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/12044 , H01L2924/15153 , H01L2924/15165 , H01L2924/16152 , H01L2924/1617 , H01L2924/16195 , H01L2924/3025
摘要： A packaged semiconductor device structure includes a semiconductor chip with an organic material covering thereon. The semiconductor chip is placed in a package and hermetically sealed with a low melting point glass. The organic covering serve to suppress undesirable influence on the semiconductor chip by .alpha.-rays which may be radiated from the package, and a getter material is placed in the package for decreasing undesirable gases in the package which may be emitted by the organic covering during the sealing process.
摘要翻译：封装的半导体器件结构包括其上覆盖有机材料的半导体芯片。将半导体芯片放置在封装中并用低熔点玻璃密封。有机覆盖物用于通过可以从封装辐射的α-射线来抑制对半导体芯片的不期望的影响，并且将吸气剂材料放置在包装中以减少包装中的不期望的气体，这可能由有机覆盖物在密封过程。

3. 发明授权

US5371713A Semiconductor integrated circuit 失效
公开(公告)号：US5371713A
公开(公告)日：1994-12-06
申请号：US207677
申请日：1994-03-09
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

4. 发明授权

US5354699A Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5354699A
公开(公告)日：1994-10-11
申请号：US964824
申请日：1992-10-22
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

5. 发明授权

US5214302A Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove 失效
标题翻译：在公共衬底上形成的半导体集成电路器件通过由沟槽隔离的场氧化物和双极晶体管隔离的MISFET
公开(公告)号：US5214302A
公开(公告)日：1993-05-25
申请号：US807411
申请日：1991-12-13
申请人： Akihisa Uchida , Keiichi Higeta , Nobuo Tamba , Masanori Odaka , Katsumi Ogiue
发明人： Akihisa Uchida , Keiichi Higeta , Nobuo Tamba , Masanori Odaka , Katsumi Ogiue
IPC分类号： H01L27/06 , H01L27/11 , H01L29/732
CPC分类号： H01L29/7325 , H01L27/0623 , H01L27/1112
摘要： A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region. The bipolar transistor is characterized as a self-alignment transistor and that the insulating side wall spacers corresponding to the gate and base (emitter) electrodes are formed by a same lever.
摘要翻译：一种半导体集成电路器件，具有以下结构，其中以下各个区域，即用于形成每个双极晶体管的基极和发射极区域的第一区域，用于形成双极性的集电极导出区域的第二区域晶体管和用于形成每个MISFET的第三区域从半导体衬底的主表面突出，由此可以实现MISFET之间以及这些MISFET与具有相同隔离结构的双极晶体管之间的隔离，并且在与双极晶体管之间的隔离相同的制造步骤。此外，在该器件中，双极晶体管的基极区域电自自对准地连接到形成在主表面上以围绕发射极区域的基极。双极晶体管的特征在于自对准晶体管，并且与栅极和基极（发射极）电极对应的绝缘侧壁间隔物由相同的杆形成。

6. 发明授权

US5512497A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US5512497A
公开(公告)日：1996-04-30
申请号：US272312
申请日：1994-07-08
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265 , H01L21/8238
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

7. 发明授权

US5311482A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5311482A
公开(公告)日：1994-05-10
申请号：US93511
申请日：1993-07-16
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
摘要翻译：为了提供高速度和低功耗，构造半导体集成电路以利用CMOS元件和双极晶体管。双极晶体管用于输出部分以利用其运行速度，以允许输出线的快速充电和放电。同时，电路的主要工作部分使用低功耗的CMOS元件。这种布置在存储器电路中是特别有利的。

8. 发明授权

US5220187A Semiconductor integrated circuit with bipolar transistors and MOSFETs 失效
标题翻译：具有双极晶体管和MOSFET的半导体集成电路
公开(公告)号：US5220187A
公开(公告)日：1993-06-15
申请号：US917907
申请日：1992-07-21
申请人： Shuuichi Miyaoka , Masanori Odaka , Katsumi Ogiue
发明人： Shuuichi Miyaoka , Masanori Odaka , Katsumi Ogiue
IPC分类号： H01L21/82 , H01L27/118 , H03K19/0944 , H03K19/173
CPC分类号： H03K19/09448 , H01L27/11896
摘要： A logic circuit to be formed in a gate array is selected depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value, and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. That is, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting such a design technique has its operating speed raised. An improved structure is also provided for reducing wiring lengths by arranging bipolar transistors in adjacent basic cells to have mirror symmetry with one another. Further, particular gate width relationships are provided between MOSFETs within basic cells for reducing propagation delay and the required occupation area.

9. 发明授权

US4858189A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4858189A
公开(公告)日：1989-08-15
申请号：US121914
申请日：1987-11-17
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
摘要翻译：为了提供高速度和低功耗，构造半导体集成电路以利用CMOS元件和双极晶体管。双极晶体管用于输出部分以利用其运行速度，以允许输出线的快速充电和放电。同时，电路的主要工作部分使用低功耗的CMOS元件。这种布置在存储器电路中是特别有利的。

10. 发明授权

US4713796A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4713796A
公开(公告)日：1987-12-15
申请号：US701226
申请日：1985-02-13
申请人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
发明人： Katsumi Ogiue , Yukio Suzuki , Ikuro Masuda , Masanori Odaka , Hideaki Uchida
IPC分类号： G11C11/413 , G11C7/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/34 , G11C11/414 , G11C11/417 , H03K19/0944
CPC分类号： G11C7/1057 , G11C7/00 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C7/12 , G11C8/00 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/09448
摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
摘要翻译：为了提供高速度和低功耗，构造半导体集成电路以利用CMOS元件和双极晶体管。双极晶体管用于输出部分以利用其运行速度，以允许输出线的快速充电和放电。同时，电路的主要工作部分使用低功耗的CMOS元件。这种布置在存储器电路中是特别有利的。

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