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1. 发明授权

US4931897A Method of manufacturing semiconductor capacitive element 失效
标题翻译：制造半导体电容元件的方法
公开(公告)号：US4931897A
公开(公告)日：1990-06-05
申请号：US390012
申请日：1989-08-07
申请人： Katsuhiro Tsukamoto , Masahiro Shimizu , Hiroshi Miyatake
发明人： Katsuhiro Tsukamoto , Masahiro Shimizu , Hiroshi Miyatake
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , Y10T29/435
摘要： A method of manufacturing a semiconductor capacitor provided with a substrate, a dielectric film formed on the substrate and a pair of electrode layers stacked on both sides of the dielectric film comprises a step of forming a polycrystalline silicon layer for serving as one of the electrode layers on the substrate, a step of making at least a surface region of the polycrystalline silicon layer amorphous, a step of forming the dielectric film on the polycrystalline silicon layer while maintaining an amorphous surface state, and a step of forming another one of the electrode layers on the dielectric film. The lower electrode of the capacitor has its surface or the whole layer made amorphous. The surface of the electrode which is amorphous has smooth surface configuration, thereby improving the quality of the dielectric film formed thereon.
摘要翻译：一种制造具有基板的半导体电容器的制造方法，在该基板上形成的电介质膜和层叠在该电介质膜的两面的一对电极层，具有形成用作电极层之一的多晶硅层的工序在所述基板上形成至少使所述多晶硅层的表面区域为非晶体的步骤，在保持非晶质表面状态的同时在所述多晶硅层上形成所述电介质膜的工序，以及形成所述电极层的另一个的工序在电介质膜上。电容器的下电极具有其表面或整个层是无定形的。无定形的电极的表面具有光滑的表面形状，从而提高其上形成的电介质膜的质量。

2. 发明授权

US4708904A Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4708904A
公开(公告)日：1987-11-24
申请号：US798639
申请日：1985-11-15
申请人： Masahiro Shimizu , Tatsuo Okamoto , Katsuhiro Tsukamoto
发明人： Masahiro Shimizu , Tatsuo Okamoto , Katsuhiro Tsukamoto
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3213 , H01L21/336 , H01L23/532 , H01L29/49 , B32B3/00 , B05D5/12 , B44C1/22 , C23C14/00
CPC分类号： H01L29/66575 , H01L21/32134 , H01L23/53257 , H01L29/4925 , H01L29/4933 , H01L2924/0002 , Y10S428/901 , Y10T428/24917
摘要： A semiconductor device and a method of manufacturing the same which comprises a semiconductor substrate and a conductive region formed thereon in multilayer structure of a film of refractory metal or refractory metal silicide inferior in corrosion resistance against a solution containing hydrofluoric acid and a film of refractory metal silicide excellent in corrosion resistance against the solution containing hydrofluorine acid and low electric resistance formed on the same.
摘要翻译：一种半导体器件及其制造方法，包括半导体衬底和形成在其上的导电区域，所述导电区域形成在难熔金属或难熔金属硅化物的多层结构中，所述多层结构耐腐蚀性低于含有氢氟酸的溶液和难熔金属膜对含有氢氟酸的溶液的耐腐蚀性优异的硅化物和在其上形成的低电阻。

3. 发明授权

US4942448A Structure for isolating semiconductor components on an integrated circuit and a method of manufacturing therefor 失效
标题翻译：用于隔离集成电路上的半导体部件的结构及其制造方法
公开(公告)号：US4942448A
公开(公告)日：1990-07-17
申请号：US262303
申请日：1988-10-25
申请人： Katsuhiro Tsukamoto , Masahide Inuishi , Masahiro Shimizu
发明人： Katsuhiro Tsukamoto , Masahide Inuishi , Masahiro Shimizu
IPC分类号： H01L21/76 , H01L21/763 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L21/76 , H01L21/763
摘要： A semiconductor apparatus having a region for isolation between devices comprises a semiconductor substrate, a polycrystalline silicon layer portions selectively formed to be spaced apart from each other on the semiconductor substrate, an impurity diffused region formed under the polycrystalline silicon layer, and a silicon oxide film for filling in a space between the respective adjacent portions of the polycrystalline silicon layer. The impurity diffused region constitutes a source or drain region of a field effect device such as a MOS transistor isolated by the silicon oxide film.
摘要翻译：具有用于在器件之间隔离的区域的半导体器件包括半导体衬底，选择性地形成为在半导体衬底上彼此间隔开的多晶硅层部分，形成在多晶硅层下面的杂质扩散区域和氧化硅膜用于填充多晶硅层的各个相邻部分之间的空间。杂质扩散区域构成诸如通过氧化硅膜隔离的MOS晶体管的场效应器件的源极或漏极区域。

4. 发明授权

US5427972A Method of making a sidewall contact 失效
标题翻译：制造侧壁接触的方法
公开(公告)号：US5427972A
公开(公告)日：1995-06-27
申请号：US511818
申请日：1990-04-18
申请人： Masahiro Shimizu , Katsuhiro Tsukamoto
发明人： Masahiro Shimizu , Katsuhiro Tsukamoto
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L23/485 , H01L27/108 , H01L29/78 , H01L21/8229
CPC分类号： H01L27/10829 , H01L21/7684 , H01L23/485 , H01L2924/0002
摘要： A semiconductor device comprises a P-type semiconductor substrate having a major surface, an insulating film formed on the major surface of the semiconductor substrate, a first polycrystalline silicon layer formed on the insulating film, an n.sup.+ diffused layer formed on the substrate and adjacent to an end portion of the first polycrystalline silicon layer, and a side wall formed on the end portion of the first polycrystalline silicon layer and formed of a second polycrystalline silicon layer for connecting the end portion of the first polycrystalline silicon layer with the n.sup.+ diffused layer.
摘要翻译：半导体器件包括具有主表面的P型半导体衬底，形成在半导体衬底的主表面上的绝缘膜，形成在绝缘膜上的第一多晶硅层，形成在衬底上并与衬底相邻的n +扩散层所述第一多晶硅层的端部和形成在所述第一多晶硅层的端部上并由用于将所述第一多晶硅层的端部与所述n +扩散层连接的第二多晶硅层形成的侧壁。

5. 发明授权

US5258321A Manufacturing method for semiconductor memory device having stacked trench capacitors and improved intercell isolation 失效
标题翻译：具有层叠沟槽电容器和改进的晶胞间隔离的半导体存储器件的制造方法
公开(公告)号：US5258321A
公开(公告)日：1993-11-02
申请号：US896872
申请日：1992-06-10
申请人： Masahiro Shimizu , Katsuhiro Tsukamoto , Masahide Inuishi
发明人： Masahiro Shimizu , Katsuhiro Tsukamoto , Masahide Inuishi
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A semiconductor memory device having memory cells formed adjacent to each other comprises a P type semiconductor substrate having adjacent two trenches, a P.sup.+ impurity region formed in the side portions and the bottom portions of the trenches, n type first polysilicon layers serving as common electrodes formed in the upper portion of the P.sup.+ impurity region through an insulating film, second polysilicon layers formed inside and in the upper portion of the trenches formed of the first polysilicon layers through an insulating film, and a third polysilicon layer formed on the second polysilicon layers, only the third polysilicon layer constituting a connecting electrode between the adjacent memory cells.
摘要翻译：具有彼此相邻形成的存储单元的半导体存储器件包括具有相邻的两个沟槽的P型半导体衬底，形成在沟槽的侧部和底部中的P +杂质区，形成用作共同电极的n型第一多晶硅层通过绝缘膜在P +杂质区的上部，通过绝缘膜形成在由第一多晶硅层形成的沟槽的内部和上部的第二多晶硅层，以及形成在第二多晶硅层上的第三多晶硅层，只有第三多晶硅层构成相邻存储单元之间的连接电极。

6. 发明授权

US4855953A Semiconductor memory device having stacked memory capacitors and method for manufacturing the same 失效
标题翻译：具有层叠存储电容器的半导体存储器件及其制造方法
公开(公告)号：US4855953A
公开(公告)日：1989-08-08
申请号：US158323
申请日：1988-02-19
申请人： Katsuhiro Tsukamoto , Masahiro Shimizu , Kazuyasu Fujishima , Yoshio Matsuda
发明人： Katsuhiro Tsukamoto , Masahiro Shimizu , Kazuyasu Fujishima , Yoshio Matsuda
IPC分类号： G11C11/404 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/417
CPC分类号： H01L27/10861 , G11C11/404 , H01L27/10829 , H01L29/41725 , H01L29/41766 , H01L29/66181
摘要： A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.
摘要翻译：动态RAM包括存储器单元的阵列，每个存储器单元包括单个存取晶体管和电荷存储区域。电荷存储区域包括第一电容器存储器，其包括形成在形成于P型硅衬底中的沟槽的内表面中的用作相对电极的P +区，形成在P +区上的第一电容器电介质膜和用于作为形成在第一电容器电介质膜上的存储器端子，以及包括公共电极层的第二存储电容器，形成在公共电极层上的第二电容器电介质膜和形成在第二电容器电介质膜上的单元板电极。存取晶体管的存储器端子和漏极区域通过具有与存储器端子的端部接触的侧壁形状的电极以自对准的方式连接。因此，不需要在第一电容器电介质膜中形成接触孔，从而可以防止第一电容器电介质膜的电可靠性的降低。存取晶体管的漏极区可以通过与公共电极层的接触部分进行自对准而形成。

7. 发明授权

US5466623A Method of making semiconductor integrated circuit having isolation oxide regions with different thickness 失效
标题翻译：制造具有不同厚度的隔离氧化物区域的半导体集成电路的方法
公开(公告)号：US5466623A
公开(公告)日：1995-11-14
申请号：US296940
申请日：1994-08-29
申请人： Masahiro Shimizu , Katsuhiro Tsukamoto
发明人： Masahiro Shimizu , Katsuhiro Tsukamoto
IPC分类号： H01L21/762 , H01L21/8239
CPC分类号： H01L21/762 , H01L21/76221 , Y10S438/981
摘要： A method of manufacturing a semiconductor memory device having a peripheral circuit portion, the operating voltage of which is relatively high and a memory array portion, the operating voltage of which is relatively low comprises the steps of forming an inversion preventing layer on the peripheral circuit portion, forming an oxide layer for isolation between-devices adjacent thereto, forming on the memory array portion the inversion preventing layer, the impurity concentration of which is higher than that of the peripheral circuit portion and forming the oxide layer on the peripheral circuit portion at the same time that the oxide layer for isolation between devices is formed adjacent thereto.
摘要翻译：一种制造半导体存储器件的方法，其具有其工作电压相对较高的外围电路部分和其工作电压相对较低的存储器阵列部分，包括在外围电路部分上形成反转防止层的步骤形成用于在与其相邻的器件之间隔离的氧化物层，在存储器阵列部分上形成反型防止层，其杂质浓度高于外围电路部分的杂质浓度，并在外围电路部分上形成氧化物层同时，用于在器件之间隔离的氧化物层与其相邻形成。

8. 发明授权

US5268321A Method of making DRAM cell having improved radiation protection 失效
标题翻译：制造具有改进的辐射防护的DRAM单元的方法
公开(公告)号：US5268321A
公开(公告)日：1993-12-07
申请号：US295101
申请日：1989-01-09
申请人： Masahiro Shimizu , Hiroki Shimano , Masahide Inuishi , Katsuhiro Tsukamoto
发明人： Masahiro Shimizu , Hiroki Shimano , Masahide Inuishi , Katsuhiro Tsukamoto
IPC分类号： H01L27/108 , H01L21/70
CPC分类号： H01L27/10805
摘要： A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n.sup.+ -type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner. Therefore, increase of interconnection resistance of the second gate electrode (3 ) and diffusion resistance of the n.sup.+ -type regions (6, 7) is prevented. A bit line is formed on the semiconductor region and connected thereto. An inner layer insulation film is optionally connected thereto. An inner layer insulation film is optionally formed between the bit line and the refractory metal silicide film placed on the semiconductor n.sup.+ -type region. The interlayer insulation film preferably comprises a silicon oxide film or a phosphorus oxide film. Finally, a protective film is optionally formed on the bit line. The protective film is preferably made of a material having a low dielectric constant.
摘要翻译：半导体存储器件包括p型半导体衬底（1），形成在其上的p +型区域（15,80），被p +型区域（15,80）包围的n +型区域（6,7）形成在n +型区域（6）中的电荷存储区域上的第一栅电极（2）和形成在p +型区域（80）上并用作字线的第二栅电极（3）。 p +型区域（15,80）防止电子从α射线诱发的电子 - 空穴对中流出，以防止软错误的发生。在第二栅电极（3）的侧壁上形成氧化膜（16），在n +型区域（6,7）上形成硅化钛膜（17），硅化钛膜（18）为以自对准的方式形成在第二栅电极（3）上。因此，防止了第二栅电极（3）的互连电阻的增加和n +型区域（6,7）的扩散电阻。在半导体区域上形成位线并与其连接。内层绝缘膜可选地连接到其上。可选地，在位线和位于半导体n +型区域上的难熔金属硅化物膜之间形成内层绝缘膜。层间绝缘膜优选包含氧化硅膜或氧化磷膜。最后，可选地在位线上形成保护膜。保护膜优选由具有低介电常数的材料制成。

9. 发明授权

US5250458A Method for manufacturing semiconductor memory device having stacked memory capacitors 失效
标题翻译：具有层叠存储电容器的半导体存储器件的制造方法
公开(公告)号：US5250458A
公开(公告)日：1993-10-05
申请号：US793971
申请日：1991-11-18
申请人： Katsuhiro Tsukamoto , Masahiro Shimizu , Kazuyasu Fujishima , Yoshio Matsuda
发明人： Katsuhiro Tsukamoto , Masahiro Shimizu , Kazuyasu Fujishima , Yoshio Matsuda
IPC分类号： G11C11/404 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/417 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10861 , G11C11/404 , H01L27/10829 , H01L29/41725 , H01L29/41766 , H01L29/66181
摘要： A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.
摘要翻译：动态RAM包括存储器单元的阵列，每个存储器单元包括单个存取晶体管和电荷存储区域。电荷存储区域包括第一电容器存储器，其包括形成在形成于P型硅衬底中的沟槽的内表面中的用作相对电极的P +区，形成在P +区上的第一电容器电介质膜和用于作为形成在第一电容器电介质膜上的存储器端子，以及包括公共电极层的第二存储电容器，形成在公共电极层上的第二电容器电介质膜和形成在第二电容器电介质膜上的单元板电极。存取晶体管的存储器端子和漏极区域通过具有与存储器端子的端部接触的侧壁形状的电极以自对准的方式连接。因此，不需要在第一电容器电介质膜中形成接触孔，从而可以防止第一电容器电介质膜的电可靠性的降低。存取晶体管的漏极区可以通过与公共电极层的接触部分进行自对准而形成。

10. 发明授权

US5478759A Method of manufacturing semiconductor device with retrograde wells 失效
标题翻译：制造具有逆行井的半导体器件的方法
公开(公告)号：US5478759A
公开(公告)日：1995-12-26
申请号：US156748
申请日：1993-11-24
申请人： Tomoharu Mametani , Masahiro Shimizu , Katsuhiro Tsukamoto , Hajime Arai , Heiji Kobayashi
发明人： Tomoharu Mametani , Masahiro Shimizu , Katsuhiro Tsukamoto , Hajime Arai , Heiji Kobayashi
IPC分类号： H01L21/761 , H01L21/265 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L21/266
CPC分类号： H01L21/823878 , H01L21/76218 , H01L27/0921 , H01L27/1052
摘要： A thick isolation oxide film is selectively formed on a surface of a silicon substrate so as to isolate an element formation region. Ions are implanted into a region in silicon substrate through the thick isolation oxide film. Thus, retrograde wells, having impurity concentration peak positions are formed in the region of silicon substrate positioned under the isolation oxide film. Then, an upper part of the isolation oxide film is removed away to form an isolation oxide film with a reduced thickness. Isolation oxide film has a reduced isolation length L. Thus, a semiconductor device is provided, which permits restriction of the narrow channel effect and the substrate biasing effect when the size of elements is reduced.
摘要翻译：在硅衬底的表面上选择性地形成厚的隔离氧化膜，以隔离元件形成区域。离子通过厚的隔离氧化膜植入到硅衬底的区域中。因此，在位于隔离氧化膜下方的硅衬底的区域中形成具有杂质浓度峰值位置的逆行阱。然后，去除隔离氧化膜的上部，形成厚度减小的隔离氧化膜。隔离氧化膜具有减小的隔离长度L.因此，提供了一种半导体器件，当元件的尺寸减小时，允许限制窄沟道效应和衬底偏置效应。

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