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1. 发明授权

US06211070B1 Peripheral structure of a chip as a semiconductor device, and manufacturing method thereof 有权
标题翻译：作为半导体器件的芯片的外围结构及其制造方法
公开(公告)号：US06211070B1
公开(公告)日：2001-04-03
申请号：US09329494
申请日：1999-06-10
申请人： Masanobu Iwasaki , Katsuhiro Tsukamoto
发明人： Masanobu Iwasaki , Katsuhiro Tsukamoto
IPC分类号： H01L214763
CPC分类号： H01L21/78 , H01L21/743
摘要： On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source•drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source•drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.
摘要翻译：在器件形成区域内的半导体衬底的表面上形成包括栅电极，栅极氧化膜和源极的MOS晶体管。绝缘层形成在半导体衬底的表面上。在源极上方的绝缘层的开口中，形成钨插塞。在切割线部分，绝缘层具有沟槽部分。沟槽部形成为围绕器件形成区域。在沟槽中形成具有与绝缘层的顶表面连续的顶表面的钨街。通过该半导体装置，能够防止接合焊盘之间的短路等，能够提高可靠性。

2. 发明授权

US5652168A Method of forming a semiconductor device having a capacitor with improved element isolation and operation rate 失效
标题翻译：一种具有电容器的半导体器件的形成方法，所述电容器具有改进的元件隔离和操作速率
公开(公告)号：US5652168A
公开(公告)日：1997-07-29
申请号：US385517
申请日：1995-02-08
申请人： Shigeki Komori , Katsuhiro Tsukamoto
发明人： Shigeki Komori , Katsuhiro Tsukamoto
IPC分类号： H01L27/04 , H01L21/02 , H01L21/285 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/41 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/28525 , H01L28/40
摘要： A lower electrode of a capacitor for use in a semiconductor device includes a first semiconductor layer having a predetermined impurity concentration and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer. As a result, intensification of an electric field at an end portion of the capacitor can be reduced. In addition, a word line is formed of a buffer layer and a main conductor layer to reduce a parasitic capacitance between the lower electrode of the capacitor and the word line.
摘要翻译：用于半导体器件的电容器的下电极包括具有预定杂质浓度的第一半导体层和杂质浓度高于第一半导体层的第二半导体层。结果，能够减小电容器端部的电场的强化。此外，字线由缓冲层和主导体层形成，以减小电容器的下电极和字线之间的寄生电容。

3. 发明授权

US5525821A PN junction trench isolation type semiconductor device 失效
标题翻译： PN结沟隔离型半导体器件
公开(公告)号：US5525821A
公开(公告)日：1996-06-11
申请号：US383672
申请日：1995-02-01
申请人： Masana Harada , Katsuhiro Tsukamoto
发明人： Masana Harada , Katsuhiro Tsukamoto
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66348 , H01L29/0619 , H01L29/0649 , H01L29/1095 , H01L29/7397 , H01L29/7813
摘要： There is disclosed a semiconductor device including a plurality of P well regions (4) and a P well region (41) insulated from each other by a plurality of trench isolating layers (10) formed regularly in predetermined spaced relation with each other and having the same depth. The outermost P well region (41) isolatedly formed externally of an outermost trench isolating layer (10A) is made as deep as the trench isolating layers (10) and, accordingly, is made deeper than the P well regions (4) except the outermost P well region (41). This provides for the alleviation of the electric field concentration generated in the bottom edge of the outermost isolating layer of trench structure, thereby achieving the semiconductor device having an improved device breakdown voltage and a method of fabricating the same.
摘要翻译：公开了一种半导体器件，其包括多个P阱区域（P阱区域）和P阱区域（P），P阱区域（41）通过以规定间隔开的关系规则形成的多个沟槽隔离层（10）彼此绝缘，并且具有相同的深度隔离地形成在最外层沟槽隔离层（10A）的外部的最外层的P阱区（41）制成与沟槽隔离层（10）一样深，因此比P阱区（4）更深，除了最外层 P井区域（41）。这提供了减轻在沟槽结构的最外隔离层的底部边缘产生的电场浓度，从而实现了具有改进的器件击穿电压的半导体器件及其制造方法。

4. 发明授权

US5457339A Semiconductor device for element isolation and manufacturing method thereof 失效
标题翻译：元件隔离半导体器件及其制造方法
公开(公告)号：US5457339A
公开(公告)日：1995-10-10
申请号：US252629
申请日：1994-06-02
申请人： Shigeki Komori , Katsuhiro Tsukamoto
发明人： Shigeki Komori , Katsuhiro Tsukamoto
IPC分类号： H01L21/76 , H01L21/763 , H01L27/08 , H01L27/04
CPC分类号： H01L21/763
摘要： A semiconductor device for element isolation comprises a semiconductor substrate having an impurity region of a first conductivity type whose impurity concentration attains the maximum at a predetermined depth from the surface in the depth direction, a trench formed to a predetermined depth in the impurity region of the first conductivity type, and an impurity diffusion region of the first conductivity type formed in the trench with an oxide film interposed and having only its bottom portion connected to the impurity region of the first conductivity type of the semiconductor substrate. In the semiconductor device, a uniform P.sup.+ high concentration region is substantially formed in a bottom portion of an isolation region, so that an isolation threshold value is not affected.
摘要翻译：用于元件隔离的半导体器件包括半导体衬底，该半导体衬底具有第一导电类型的杂质区域，其杂质浓度在与深度方向的表面相距预定深度处达到最大值，在该杂质区域中形成预定深度的沟槽第一导电类型和沟槽中形成的第一导电类型的杂质扩散区域，其中氧化膜被插入并且仅其底部部分连接到半导体衬底的第一导电类型的杂质区域。在半导体装置中，在隔离区域的底部大致形成均匀的P +高浓度区域，从而不影响隔离阈值。

5. 发明授权

US5401671A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5401671A
公开(公告)日：1995-03-28
申请号：US167280
申请日：1993-12-15
申请人： Shigeki Komori , Katsuhiro Tsukamoto
发明人： Shigeki Komori , Katsuhiro Tsukamoto
IPC分类号： H01L21/761 , H01L21/74 , H01L21/76 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L21/265
CPC分类号： H01L21/74 , H01L27/0921 , H01L27/0928 , H01L27/10808
摘要： A semiconductor device has an upper well of a first conductivity type formed from the surface of an active region separated by an isolation oxide film at the surface of a semiconductor substrate to a predetermined depth. A first conductivity type layer of high concentration is formed along the entire region of an active region to enclose the bottom of the upper well of the first conductivity type. A lower well of the first conductivity type of a predetermined thickness is formed as a buried layer to enclose the bottom of the first conductivity type layer of high concentration. According to this structure, the spreadout of impurities into the active region due to diffusion at the time of thermal treatment is suppressed. The semiconductor device has the wells and the buried layer of high concentration formed by implanting impurities after the step of forming the isolation oxide film, so that diffusion of impurities into the active region due to thermal treatment at the time of isolation oxide film formation is suppressed. As a result, degradation of channel effect is prevented in miniaturization of the semiconductor device.
摘要翻译：半导体器件具有由半导体衬底的表面上的隔离氧化膜分隔成预定深度的由有源区的表面形成的第一导电类型的上阱。沿着有源区域的整个区域形成高浓度的第一导电型层，以包围第一导电类型的上阱的底部。形成预定厚度的第一导电类型的下阱作为掩埋层以包围高浓度的第一导电类型层的底部。根据该结构，能够抑制由于热处理时的扩散而使杂质向活性区域的扩散。半导体器件具有在形成隔离氧化膜的步骤之后通过注入杂质形成的阱和高浓度的掩埋层，从而抑制了隔离氧化膜形成时由于热处理而导致的杂质向有源区的扩散。结果，半导体器件的小型化防止沟道效应的劣化。

6. 发明授权

US5141882A Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor 失效
标题翻译：具有在井中形成的通道停止和通道区域的半导体场效应器件及其制造方法
公开(公告)号：US5141882A
公开(公告)日：1992-08-25
申请号：US816546
申请日：1991-12-30
申请人： Shigeki Komori , Katsuhiro Tsukamoto
发明人： Shigeki Komori , Katsuhiro Tsukamoto
IPC分类号： H01L21/266 , H01L21/762 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/76218 , H01L21/266 , H01L21/823892 , H01L27/0928
摘要： A method of forming a well on a semiconductor substrate and a transistor on the main surface of this well. A mask exposing a region for the well is formed on the main surface of the semiconductor substrate. Subsequently, ions of impurities for forming the well are implanted on the main surface of the region for the well of the semiconductor substrate using this mask with high energy giving concentration distribution of impurities which becomes maximum at a place deeper than a region for a transistor. Subsequently, ions of impurities of the same conductivity type as that of ions for forming the well are implanted on the main surface of the region for the well of the semiconductor substrate using the mask with low energy giving concentration distribution of impurities in which impurities stay in the region for the channel of the transistor. According to this method, since the formation of the well and channel ion implantation are performed using the same mask, the number of photolithography processes is decreased. In addition, in forming the well, since it is not necessary to diffuse the impurity ions by heat, manufacturing time can be shortened. In addition, since ions of impurities are implanted in the channel region of the transistor, a punch through of the transistor can be prevented.
摘要翻译：在该阱的主表面上的半导体衬底和晶体管上形成阱的方法。在半导体基板的主表面上形成露出用于阱的区域的掩模。接着，使用该掩膜，在半导体衬底的阱的区域的主表面上注入用于形成阱的离子，从而在比晶体管的区域更深的位置处产生最大的杂质浓度分布。随后，使用具有低能量的掩模，在半导体衬底的阱的区域的主表面上注入与用于形成阱的离子相同的导电类型的杂质的离子，得到杂质保持在其中的杂质的浓度分布晶体管通道的区域。根据该方法，由于使用相同的掩模进行阱和沟道离子注入的形成，所以光刻工序的数量减少。此外，在形成阱时，由于不需要通过加热来扩散杂质离子，因此可以缩短制造时间。此外，由于杂质的离子注入在晶体管的沟道区域中，所以可以防止晶体管的穿通。

7. 发明授权

US5047818A Semiconductor memory device having buried structure to suppress soft errors 失效
标题翻译：具有掩埋结构以抑制软错误的半导体存储器件
公开(公告)号：US5047818A
公开(公告)日：1991-09-10
申请号：US662989
申请日：1991-02-28
申请人： Katsuhiro Tsukamoto
发明人： Katsuhiro Tsukamoto
IPC分类号： H01L29/78 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10805
摘要： A semiconductor memory device comprises a capacitor and a transistor formed on a main surface of a semiconductor substrate and a buried layer of high impurity concentration formed in the substrate, wherein the buried layer has the same conductivity type as that of the substrate and is formed shallow under the capacitor and deep under the transistor.
摘要翻译：半导体存储器件包括电容器和形成在半导体衬底的主表面上的晶体管和形成在衬底中的高杂质浓度的掩埋层，其中掩埋层具有与衬底相同的导电类型并形成浅在电容器下面和深深的晶体管下面。

8. 发明授权

US4708904A Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4708904A
公开(公告)日：1987-11-24
申请号：US798639
申请日：1985-11-15
申请人： Masahiro Shimizu , Tatsuo Okamoto , Katsuhiro Tsukamoto
发明人： Masahiro Shimizu , Tatsuo Okamoto , Katsuhiro Tsukamoto
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3213 , H01L21/336 , H01L23/532 , H01L29/49 , B32B3/00 , B05D5/12 , B44C1/22 , C23C14/00
CPC分类号： H01L29/66575 , H01L21/32134 , H01L23/53257 , H01L29/4925 , H01L29/4933 , H01L2924/0002 , Y10S428/901 , Y10T428/24917
摘要： A semiconductor device and a method of manufacturing the same which comprises a semiconductor substrate and a conductive region formed thereon in multilayer structure of a film of refractory metal or refractory metal silicide inferior in corrosion resistance against a solution containing hydrofluoric acid and a film of refractory metal silicide excellent in corrosion resistance against the solution containing hydrofluorine acid and low electric resistance formed on the same.
摘要翻译：一种半导体器件及其制造方法，包括半导体衬底和形成在其上的导电区域，所述导电区域形成在难熔金属或难熔金属硅化物的多层结构中，所述多层结构耐腐蚀性低于含有氢氟酸的溶液和难熔金属膜对含有氢氟酸的溶液的耐腐蚀性优异的硅化物和在其上形成的低电阻。

9. 发明授权

US4441932A Process for preparing semiconductor device having active base region implanted therein using walled emitter opening and the edge of dielectric isolation zone 失效
标题翻译：使用壁式发射器开口和电介质隔离区的边缘来制备其中注入有活性碱性区的半导体器件的方法
公开(公告)号：US4441932A
公开(公告)日：1984-04-10
申请号：US357299
申请日：1982-03-11
申请人： Yoichi Akasaka , Katsuhiro Tsukamoto
发明人： Yoichi Akasaka , Katsuhiro Tsukamoto
IPC分类号： H01L21/76 , H01L21/027 , H01L21/265 , H01L21/331 , H01L21/763 , H01L29/08 , H01L29/10 , H01L29/73 , H01L21/225 , H01L21/26
CPC分类号： H01L29/66272 , H01L21/0271 , H01L21/26513 , H01L21/2652 , H01L21/763 , H01L29/0804 , H01L29/1004
摘要： A process for preparing a semiconductor device having a walled emitter structure covering at least one side surface with a dielectric layer for separation of devices comprises a step of forming a base by implantation of ions with a resist mask for base; a step of forming an emitter by implantation of ions from an emitter-opening part; and a step of formation an active base in a base just below said emitter by implantation of ions from said emitter-opening part.
摘要翻译：一种半导体器件的制造方法，其具有覆盖至少一个侧面的具有壁状发射极结构的电介质层，用于分离器件包括通过用基底的抗蚀剂掩模注入离子形成基底的步骤; 通过从发射开口部分注入离子形成发射体的步骤; 以及通过从所述发射体开口部分注入离子，在刚好在所述发射体正下方的基底中形成活性碱的步骤。

10. 发明授权

US5883408A Semiconductor memory device and method for making the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5883408A
公开(公告)日：1999-03-16
申请号：US296988
申请日：1994-08-26
申请人： Katsuhiro Tsukamoto
发明人： Katsuhiro Tsukamoto
IPC分类号： H01L29/78 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10805
摘要： A semiconductor memory device comprises a capacitor and a transistor formed on a main surface of a semiconductor substrate and a buried layer of high impurity concentration formed in the substrate, wherein the buried layer has the same conductivity type as that of the substrate and is formed shallow under the capacitor and deep under the transistor.
摘要翻译：半导体存储器件包括电容器和形成在半导体衬底的主表面上的晶体管和形成在衬底中的高杂质浓度的掩埋层，其中掩埋层具有与衬底相同的导电类型并形成浅在电容器下面和深深的晶体管下面。

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