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1. 发明授权

US06798276B2 Reduced potential generation circuit operable at low power-supply potential 失效
标题翻译：减少在低电源电位下工作的电位产生电路
公开(公告)号：US06798276B2
公开(公告)日：2004-09-28
申请号：US10217408
申请日：2002-08-14
申请人： Katsuhiro Mori , Shinya Fujioka , Jun Ohno
发明人： Katsuhiro Mori , Shinya Fujioka , Jun Ohno
IPC分类号： G05F110
CPC分类号： G05F3/262
摘要： A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.
摘要翻译：电源电路包括将第一电位与第二电位进行比较的第一NMOS型电流镜电路和将第一电位与第三电位进行比较的第二NMOS型电流镜电路和调整第一电位的电位设定电路响应于第一和第二NMOS型电流镜电路的输出的电位，使得第一电位落在第二电位和第三电位之间。

2. 发明授权

US06473347B2 Semiconductor device having memory with effective precharging scheme 有权
标题翻译：具有具有有效预充电方案的存储器的半导体器件
公开(公告)号：US06473347B2
公开(公告)日：2002-10-29
申请号：US09929354
申请日：2001-08-15
申请人： Katsuhiro Mori , Shinya Fujioka , Akihiro Funya
发明人： Katsuhiro Mori , Shinya Fujioka , Akihiro Funya
IPC分类号： G11C7100
CPC分类号： G11C29/50 , G11C8/08 , G11C11/401
摘要： A semiconductor device includes a plurality of word lines selectable in a predetermined mode, and a circuit that precharges the plurality of word lines selected in the predetermined mode in a time division manner.
摘要翻译：半导体器件包括以预定模式可选择的多个字线，以及以时分方式对以预定模式选择的多个字线进行预充电的电路。

3. 发明授权

US06621750B2 Semiconductor memory 有权
公开(公告)号：US06621750B2
公开(公告)日：2003-09-16
申请号：US10155029
申请日：2002-05-28
申请人： Yoshiaki Okuyama , Shinya Fujioka , Kota Hara , Katsuhiro Mori
发明人： Yoshiaki Okuyama , Shinya Fujioka , Kota Hara , Katsuhiro Mori
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812 , G11C29/848
摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

4. 发明授权

US06566937B1 Fuse circuit 有权
标题翻译：保险丝电路
公开(公告)号：US06566937B1
公开(公告)日：2003-05-20
申请号：US10152579
申请日：2002-05-23
申请人： Katsuhiro Mori , Shinya Fujioka , Masahiro Niimi
发明人： Katsuhiro Mori , Shinya Fujioka , Masahiro Niimi
IPC分类号： H01H3776
CPC分类号： G11C17/16
摘要： Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.
摘要翻译：在第一周期的前半段通过第三开关接收到第二节点的电平时，保持电路将其作为指示保险丝的熔断状态的熔丝信号输出。由于在第一周期的后半部分中第三开关断开，所以其后发生的第二节点的电平变化不会影响保持电路中的数据，从而防止熔丝电路的故障。在保险丝熔断时，在第一周期之后，第一节点的电平固定在第二电源线的电平上。这消除了保险丝两端之间的电压差，从而防止了长时间的恢复。即使没有完全切断保险丝，也不会发生长时间退回，只有一个保险丝对保险丝电路充足。从而缩短了在测试过程中熔断熔断器的时间。

5. 发明授权

US06759866B2 Semiconductor integrated circuit and a testing method thereof 失效
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US06759866B2
公开(公告)日：2004-07-06
申请号：US10274602
申请日：2002-10-22
申请人： Katsuhiro Mori , Shinya Fujioka
发明人： Katsuhiro Mori , Shinya Fujioka
IPC分类号： G01R3128
CPC分类号： G01R31/3004 , G01R31/31721
摘要： Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.
摘要翻译：半导体集成电路的工作裕度通过在正常操作模式之间切换电源电路而被可靠地测试，其中第一升压电源用于存储器核心和降压电源，以及测试模式，其中存储器核心由外部测试电源供电，为测试提供波动的电压，降压电源由第二升压电源供电。

6. 发明授权

US06683491B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06683491B2
公开(公告)日：2004-01-27
申请号：US10106107
申请日：2002-03-27
申请人： Toru Koga , Shinya Fujioka , Katsuhiro Mori
发明人： Toru Koga , Shinya Fujioka , Katsuhiro Mori
IPC分类号： G05F110
CPC分类号： G11C11/4074 , G11C2207/2227
摘要： First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.
摘要翻译：第一和第二电压发生器产生分别提供给第一内部电源线和第二内部电源电压的第一内部电源电压以供给第二内部电源线。当第一和第二电压发生器的操作被暂停时，短路使第一和第二内部电源线短路。第一和第二内部电源线变为浮动，并且各个内部电源线中存储的电荷逐渐排出。这里，由于电荷被重新分配给两个内部电源线，所以第一和第二内部电源电压随着它们的下降而变得相等。因此，可以防止第一和第二内部电源电压反转，并且可以防止连接到第一和第二内部电源线的内部电路发生故障。

7. 发明授权

US07032142B2 Memory circuit having parity cell array 失效
公开(公告)号：US07032142B2
公开(公告)日：2006-04-18
申请号：US10271533
申请日：2002-10-17
申请人： Shinya Fujioka , Waichiro Fujieda , Kota Hara , Toru Koga , Katsuhiro Mori
发明人： Shinya Fujioka , Waichiro Fujieda , Kota Hara , Toru Koga , Katsuhiro Mori
IPC分类号： G11C29/00 , G11C7/00 , G06F11/00
CPC分类号： G11C29/42 , G06F11/106 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C2211/4062
摘要： A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

8. 发明授权

US07903487B2 Semiconductor memory device, and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US07903487B2
公开(公告)日：2011-03-08
申请号：US12201922
申请日：2008-08-29
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译：内部电压发生器激活时，产生内部电压供给内部电路。操作内部电压发生器消耗预定量的功率。响应来自外部的控制信号，入口电路使内部电压发生器失活。内部电压发生器未激活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器记忆细胞。

9. 发明授权

US07869296B2 Semiconductor memory device, and method of controlling the same 有权
公开(公告)号：US07869296B2
公开(公告)日：2011-01-11
申请号：US11515852
申请日：2006-09-06
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

10. 发明授权

US07848176B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07848176B2
公开(公告)日：2010-12-07
申请号：US12428828
申请日：2009-04-23
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

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