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1. 发明授权

US06798276B2 Reduced potential generation circuit operable at low power-supply potential 失效
标题翻译：减少在低电源电位下工作的电位产生电路
公开(公告)号：US06798276B2
公开(公告)日：2004-09-28
申请号：US10217408
申请日：2002-08-14
申请人： Katsuhiro Mori , Shinya Fujioka , Jun Ohno
发明人： Katsuhiro Mori , Shinya Fujioka , Jun Ohno
IPC分类号： G05F110
CPC分类号： G05F3/262
摘要： A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.
摘要翻译：电源电路包括将第一电位与第二电位进行比较的第一NMOS型电流镜电路和将第一电位与第三电位进行比较的第二NMOS型电流镜电路和调整第一电位的电位设定电路响应于第一和第二NMOS型电流镜电路的输出的电位，使得第一电位落在第二电位和第三电位之间。

2. 发明授权

US06759866B2 Semiconductor integrated circuit and a testing method thereof 失效
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US06759866B2
公开(公告)日：2004-07-06
申请号：US10274602
申请日：2002-10-22
申请人： Katsuhiro Mori , Shinya Fujioka
发明人： Katsuhiro Mori , Shinya Fujioka
IPC分类号： G01R3128
CPC分类号： G01R31/3004 , G01R31/31721
摘要： Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.
摘要翻译：半导体集成电路的工作裕度通过在正常操作模式之间切换电源电路而被可靠地测试，其中第一升压电源用于存储器核心和降压电源，以及测试模式，其中存储器核心由外部测试电源供电，为测试提供波动的电压，降压电源由第二升压电源供电。

3. 发明授权

US06683491B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06683491B2
公开(公告)日：2004-01-27
申请号：US10106107
申请日：2002-03-27
申请人： Toru Koga , Shinya Fujioka , Katsuhiro Mori
发明人： Toru Koga , Shinya Fujioka , Katsuhiro Mori
IPC分类号： G05F110
CPC分类号： G11C11/4074 , G11C2207/2227
摘要： First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.
摘要翻译：第一和第二电压发生器产生分别提供给第一内部电源线和第二内部电源电压的第一内部电源电压以供给第二内部电源线。当第一和第二电压发生器的操作被暂停时，短路使第一和第二内部电源线短路。第一和第二内部电源线变为浮动，并且各个内部电源线中存储的电荷逐渐排出。这里，由于电荷被重新分配给两个内部电源线，所以第一和第二内部电源电压随着它们的下降而变得相等。因此，可以防止第一和第二内部电源电压反转，并且可以防止连接到第一和第二内部电源线的内部电路发生故障。

4. 发明授权

US07032142B2 Memory circuit having parity cell array 失效
公开(公告)号：US07032142B2
公开(公告)日：2006-04-18
申请号：US10271533
申请日：2002-10-17
申请人： Shinya Fujioka , Waichiro Fujieda , Kota Hara , Toru Koga , Katsuhiro Mori
发明人： Shinya Fujioka , Waichiro Fujieda , Kota Hara , Toru Koga , Katsuhiro Mori
IPC分类号： G11C29/00 , G11C7/00 , G06F11/00
CPC分类号： G11C29/42 , G06F11/106 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C2211/4062
摘要： A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

5. 发明授权

US06473347B2 Semiconductor device having memory with effective precharging scheme 有权
标题翻译：具有具有有效预充电方案的存储器的半导体器件
公开(公告)号：US06473347B2
公开(公告)日：2002-10-29
申请号：US09929354
申请日：2001-08-15
申请人： Katsuhiro Mori , Shinya Fujioka , Akihiro Funya
发明人： Katsuhiro Mori , Shinya Fujioka , Akihiro Funya
IPC分类号： G11C7100
CPC分类号： G11C29/50 , G11C8/08 , G11C11/401
摘要： A semiconductor device includes a plurality of word lines selectable in a predetermined mode, and a circuit that precharges the plurality of word lines selected in the predetermined mode in a time division manner.
摘要翻译：半导体器件包括以预定模式可选择的多个字线，以及以时分方式对以预定模式选择的多个字线进行预充电的电路。

6. 发明授权

US06621750B2 Semiconductor memory 有权
公开(公告)号：US06621750B2
公开(公告)日：2003-09-16
申请号：US10155029
申请日：2002-05-28
申请人： Yoshiaki Okuyama , Shinya Fujioka , Kota Hara , Katsuhiro Mori
发明人： Yoshiaki Okuyama , Shinya Fujioka , Kota Hara , Katsuhiro Mori
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812 , G11C29/848
摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

7. 发明授权

US06566937B1 Fuse circuit 有权
标题翻译：保险丝电路
公开(公告)号：US06566937B1
公开(公告)日：2003-05-20
申请号：US10152579
申请日：2002-05-23
申请人： Katsuhiro Mori , Shinya Fujioka , Masahiro Niimi
发明人： Katsuhiro Mori , Shinya Fujioka , Masahiro Niimi
IPC分类号： H01H3776
CPC分类号： G11C17/16
摘要： Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.
摘要翻译：在第一周期的前半段通过第三开关接收到第二节点的电平时，保持电路将其作为指示保险丝的熔断状态的熔丝信号输出。由于在第一周期的后半部分中第三开关断开，所以其后发生的第二节点的电平变化不会影响保持电路中的数据，从而防止熔丝电路的故障。在保险丝熔断时，在第一周期之后，第一节点的电平固定在第二电源线的电平上。这消除了保险丝两端之间的电压差，从而防止了长时间的恢复。即使没有完全切断保险丝，也不会发生长时间退回，只有一个保险丝对保险丝电路充足。从而缩短了在测试过程中熔断熔断器的时间。

8. 发明授权

US08613982B2 Method of producing coated lenses 有权
标题翻译：生产涂层镜片的方法
公开(公告)号：US08613982B2
公开(公告)日：2013-12-24
申请号：US12516740
申请日：2008-01-25
申请人： Naoto Takahashi , Katsuhiro Mori , Noriyuki Fukada
发明人： Naoto Takahashi , Katsuhiro Mori , Noriyuki Fukada
IPC分类号： C08J7/04 , C08F2/48
CPC分类号： B05D1/005 , B05D3/067 , B05D5/061
摘要： A method of coating without permitting the coating solution to flow onto the side surfaces or the back surfaces of the lenses in the operation for applying the coating solution onto the lenses. A lens 15 is spin-coated with the coating solution having a particular viscosity. A side edge portion 121 of a spatula 119 is brought into contact with an upper edge portion of a side surface 15a of the lens 15 before the coating solution fed onto the surface of the lens arrives at the peripheral edge portion of the lens. The side edge portion 121 of the spatula 119 is so arranged that the upper end side of the spatula is tilted toward the center side of the lens 15 at an angle of 5 to 35 degrees with the vertical line as a reference. The coating solution applied onto the lens 15 that is rotating adheres onto the spatula 119 but does not adhere onto the side surface of the lens 15.
摘要翻译：在涂布溶液到透镜的操作中，涂布方法不允许涂布溶液流到透镜的侧表面或背面。透镜15被涂覆有具有特定粘度的涂布溶液。刮刀119的侧边缘部分121与透镜15的侧表面15a的上边缘部分接触，然后将馈送到透镜表面的涂布溶液到达透镜的周缘部分。刮铲119的侧边缘部分121被布置成使得刮刀的上端侧以垂直线作为基准以5至35度的角度朝向透镜15的中心侧倾斜。施加到正在旋转的透镜15上的涂布溶液粘附到刮刀119上，但不粘附到透镜15的侧表面上。

9. 发明申请

US20130215488A1 Photochromic Composition 有权
标题翻译：光致变色组合物
公开(公告)号：US20130215488A1
公开(公告)日：2013-08-22
申请号：US13814254
申请日：2011-08-04
申请人： Toshimitsu Hiraren , Katsuhiro Mori , Yasutomo Shimizu
发明人： Toshimitsu Hiraren , Katsuhiro Mori , Yasutomo Shimizu
IPC分类号： G02B1/04 , G02B5/23
CPC分类号： G02B1/04 , C09K9/02 , C09K2211/1007 , C09K2211/1011 , C09K2211/1033 , C09K2211/1088 , G02B5/23
摘要： A photochromic composition, which can function as an adhesive layer for bonding optical sheets made from a polycarbonate resin, may include a polyurethane-urea resin (A) obtained by reacting a polyol compound (A1), a polyisocyante compound (A2) that has two or more isocyanato groups in the molecule, and an amino-containing compound (A3) that contains two or more isocyanato-reactive groups in the molecule, with at least one of the isocyanato-reactive groups being an amino group; and a photochromic compound (B).
摘要翻译：作为用于粘合由聚碳酸酯树脂制成的光学片的粘合剂层的光致变色组合物可以包括通过使多元醇化合物（A1），多异氰酸酯化合物（A2）与二元醇化合物（A2）反应得到的聚氨酯 - 脲树脂（A）或更多的分子中的异氰酸根合基团，和分子中含有两个或多个异氰酸酯基反应性基团的含氨基化合物（A3），其中至少一个异氰酸酯基反应性基团是氨基; 和光致变色化合物（B）。

10. 发明授权

US08440267B2 Method of manufacturing laminated body 有权
标题翻译：层压体的制造方法
公开(公告)号：US08440267B2
公开(公告)日：2013-05-14
申请号：US10547725
申请日：2004-03-04
申请人： Katsuhiro Mori , Junji Momoda , Naoto Takahashi
发明人： Katsuhiro Mori , Junji Momoda , Naoto Takahashi
IPC分类号： C08F2/48
CPC分类号： B05D3/067 , B05D1/002 , B05D3/0486 , B05D5/061 , G02B1/105 , G02B1/14 , G02B1/16
摘要： A process for efficiently forming a thick coating layer having a uniform thickness on the surface of a base material having a curved surface. The process comprises the steps of forming a coating film having a predetermined thickness by applying a coating agent containing a polymerizable monomer on the curved surface of a base material, and then curing the coating film in an atmosphere of an oxygen concentration of not more than 500 ppm by photo-polymerization while substantially maintaining the uniformity of the thickness of the coating film. Preferably, the photo-polymerization of the coating film is carried out while rotating the base material at a rotational speed of from 20 to 1500 rpm.
摘要翻译：在具有弯曲表面的基材的表面上有效地形成具有均匀厚度的厚涂层的方法。该方法包括以下步骤：通过在基材的曲面上涂布含有聚合性单体的涂布剂，形成具有规定厚度的涂膜，然后在氧浓度为500以下的气氛中使涂膜固化通过光聚合，同时基本上保持涂膜厚度的均匀性。优选地，在以20-1500rpm的转速旋转基材的同时进行涂膜的光聚合。

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