会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明申请
    • Semiconductor Devices, Assemblies And Constructions
    • 半导体器件,组件和结构
    • US20110316091A1
    • 2011-12-29
    • US13224804
    • 2011-09-02
    • Ted TaylorXiawan Yang
    • Ted TaylorXiawan Yang
    • H01L27/088
    • H01L21/76283
    • Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    • 本文公开的实施例包括其中一对开口形成为半导体材料的方法,其中开口通过半导体材料的部分彼此间隔开。 衬套沿着开口的侧壁形成,然后半导体材料从开口的底部被各向同性地蚀刻以合并开口,从而完全地切割半导体材料段。 本文公开的实施例可以用于形成SOI结构,并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。 本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。
    • 7. 发明授权
    • Method and apparatus for detecting defects in the manufacture of an electronic device
    • 用于检测电子设备制造中的缺陷的方法和装置
    • US06452677B1
    • 2002-09-17
    • US09023925
    • 1998-02-13
    • Douglas DoTed Taylor
    • Douglas DoTed Taylor
    • G01B1100
    • G01N21/95684Y10S977/773
    • The invention provides a unique method and apparatus for detecting defects in an electronic device. In one preferred embodiment, the electronic device is a semiconductor integrated circuit (IC), particularly one of a plurality of IC dies fabricated on a wafer of silicon or other semiconductor material. The defect detection operation is effectuated by a unique combination of critical dimension measurement and pattern defect inspection techniques. During the initial scan of the surface of the wafer, in an attempt to locate the appropriate area for a critical dimension (CD) feature or element that is to be measured, a “best fit” comparison is made between a reference image and scanned images. The critical dimension measurements are conducted on a “best fit” image. In addition, a “worst fit” comparison is made between the reference and scanned images. A “worst fit” determination represents pattern distortions or defects in the ICs under evaluation.
    • 本发明提供了一种用于检测电子设备中的缺陷的独特方法和装置。 在一个优选实施例中,电子器件是半导体集成电路(IC),特别是在硅或其他半导体材料的晶片上制造的多个IC管芯中的一个。 缺陷检测操作通过关键尺寸测量和图案缺陷检测技术的独特组合来实现。 在晶片表面的初始扫描期间,为了定位要测量的关键尺寸(CD)特征或元件的适当区域,在参考图像和扫描图像之间进行“最佳拟合”比较 。 关键尺寸测量在“最佳拟合”图像上进行。 此外,在参考和扫描图像之间进行“最差拟合”比较。 “最差拟合”确定表示评估中的IC中的模式失真或缺陷。
    • 8. 发明申请
    • Transistors, Semiconductor Devices, Assemblies And Constructions
    • 晶体管,半导体器件,组件和结构
    • US20090200614A1
    • 2009-08-13
    • US12424392
    • 2009-04-15
    • Ted TaylorXiawan Yang
    • Ted TaylorXiawan Yang
    • H01L27/088
    • H01L21/76283
    • Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    • 本文公开的实施例包括其中一对开口形成为半导体材料的方法,其中开口通过半导体材料的部分彼此间隔开。 衬套沿着开口的侧壁形成,然后半导体材料从开口的底部被各向同性地蚀刻以合并开口,从而完全地切割半导体材料段。 本文公开的实施例可以用于形成SOI结构,并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。 本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。
    • 9. 发明申请
    • Selective etch chemistries for forming high aspect ratio features and associated structures
    • 用于形成高纵横比特征和相关结构的选择性蚀刻化学
    • US20080057724A1
    • 2008-03-06
    • US11515435
    • 2006-08-31
    • Mark KiehlbauchTed Taylor
    • Mark KiehlbauchTed Taylor
    • H01L21/461H01L21/302
    • H01L21/31116
    • An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x≧1, y≧0 and z≧0. The carbon species can be generated from a carbon compound, such as CαMβHγ, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and α≧1, β≧0 and γ≧0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.
    • 使用包括硅物质和卤化物物质以及还优选碳物质和氧物质的等离子体蚀刻化学品来选择性地蚀刻诸如氧化硅层的层间电介质层。 硅物质可以由硅化合物生成,例如Si x为硅,“M”为硅,“M” “是一种或多种卤素,”H“是氢,x> = 1,y> = 0且z> = 0。 碳物质可以由碳化合物生成,例如C a为C的C“C”,“M” “是一种或多种卤素,”H“是氢,α> = 1,β> = 0和γ> = 0。 氧类可以由氧化合物(例如O 2)生成,其可以与碳反应形成挥发性化合物。