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1. 发明授权

US08053823B2 Simplified buried plate structure and process for semiconductor-on-insulator chip 有权
标题翻译：半导体绝缘体芯片的简化掩埋板结构和工艺
公开(公告)号：US08053823B2
公开(公告)日：2011-11-08
申请号：US10906808
申请日：2005-03-08
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Carl J. Radens
IPC分类号： H01L27/108
CPC分类号： H01L21/84 , H01L27/10864 , H01L27/10867 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.
摘要翻译：本文提供了一种结构，其包括具有设置在SOI衬底的掩埋氧化物层下方的至少部分的沟槽电容器阵列。每个沟槽电容器共享共同的单一掩埋电容器板，其包括设置在掩埋氧化物层下方的第一单一半导体区域的至少一部分。掩埋电容器板的上边界限定平行于衬底的主表面的平面，横向延伸穿过整个沟槽电容器阵列。在从SOI或体衬底开始的特定实施例中，阵列的沟槽和接触孔同时形成，使得接触孔延伸到与沟槽基本相同的深度。接触孔优选地具有比沟槽更大的宽度，使得可以通过用于形成沿着沟槽的壁延伸的沟槽电容器的处理同时形成导电接触通孔。

2. 发明授权

US07759188B2 Method of fabricating vertical body-contacted SOI transistor 失效
标题翻译：垂直体接触SOI晶体管的制造方法
公开(公告)号：US07759188B2
公开(公告)日：2010-07-20
申请号：US12002828
申请日：2007-12-19
申请人： Kangguo Cheng , Gary B. Bronner , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Gary B. Bronner , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译：提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域的沟渠衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

3. 发明授权

US07737482B2 Self-aligned strap for embedded trench memory on hybrid orientation substrate 失效
标题翻译：用于混合取向基板上嵌入式沟槽存储器的自对准带
公开(公告)号：US07737482B2
公开(公告)日：2010-06-15
申请号：US11538982
申请日：2006-10-05
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L27/1207 , H01L29/78
摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.
摘要翻译：公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。在一个实施例中，带是硅化物带。

4. 发明申请

US20090176339A1 Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
标题翻译：在单元中并联连接沟槽电容器的多端口存储器制造方法
公开(公告)号：US20090176339A1
公开(公告)日：2009-07-09
申请号：US12316748
申请日：2008-12-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译：提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

5. 发明授权

US07439559B2 SOI device with different crystallographic orientations 有权
标题翻译：具有不同晶体取向的SOI器件
公开(公告)号：US07439559B2
公开(公告)日：2008-10-21
申请号：US11469039
申请日：2006-08-31
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/74
CPC分类号： H01L29/78642 , H01L27/10864 , H01L27/1087
摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.
摘要翻译：在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

6. 发明申请

US20080083941A1 SELF-ALIGNED STRAP FOR EMBEDDED TRENCH MEMORY ON HYBRID ORIENTATION SUBSTRATE 失效
标题翻译：用于混合定向衬底上嵌入式TRENCH存储器的自对准层
公开(公告)号：US20080083941A1
公开(公告)日：2008-04-10
申请号：US11538982
申请日：2006-10-05
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L27/1207 , H01L29/78
摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.
摘要翻译：公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。在一个实施例中，带是硅化物带。

7. 发明授权

US08779511B2 Integration of fin-based devices and ETSOI devices 有权
标题翻译：集成了鳍式设备和ETSOI设备
公开(公告)号：US08779511B2
公开(公告)日：2014-07-15
申请号：US13530887
申请日：2012-06-22
申请人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/088
CPC分类号： H01L27/1211 , H01L21/845
摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.
摘要翻译：薄半导体区域和厚半导体区域被形成为绝缘体层。厚半导体区域包括至少一个半导体鳍片。图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。此外，翅片源极和漏极区域在薄的鳍部上生长。源极和漏极区域，鳍片和一次性栅电极被平坦化。一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

8. 发明授权

US07485525B2 Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell 失效
标题翻译：制造在单元中具有多个并联连接的沟槽电容器的多端口存储器的方法
公开(公告)号：US07485525B2
公开(公告)日：2009-02-03
申请号：US11306749
申请日：2006-01-10
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

9. 发明授权

US07223669B2 Structure and method for collar self-aligned to buried plate 失效
标题翻译：套圈自对准埋地板的结构与方法
公开(公告)号：US07223669B2
公开(公告)日：2007-05-29
申请号：US10710061
申请日：2004-06-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L21/20
CPC分类号： H01L21/3081 , H01L27/10864 , H01L27/10867 , H01L27/1087
摘要： A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.
摘要翻译：提供一种用于形成围绕半导体衬底中的沟槽的一部分的环的结构和方法，所述套环具有与邻近所述沟槽的下部设置的掩埋板的顶部边缘自对准的下边缘。

10. 发明授权

US09059000B2 Methods and structures for protecting one area while processing another area on a chip 有权
公开(公告)号：US09059000B2
公开(公告)日：2015-06-16
申请号：US12106586
申请日：2008-04-21
申请人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , G03F7/11
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

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