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1. 发明申请

US20120306015A1 CONTACTS FOR FET DEVICES 审中-公开
标题翻译： FET器件的接触
公开(公告)号：US20120306015A1
公开(公告)日：2012-12-06
申请号：US13562355
申请日：2012-07-31
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A device characterized as being an FET device structure with enlarged contact areas is disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide layer on its top surface and on its sidewall surface.
摘要翻译：公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触物接合在其顶表面及其侧壁表面上的硅化物层。

2. 发明申请

US20120112279A1 CONTACTS FOR FET DEVICES 有权
标题翻译： FET器件的接触
公开(公告)号：US20120112279A1
公开(公告)日：2012-05-10
申请号：US12941042
申请日：2010-11-06
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L29/772 , H01L29/45 , H01L21/28
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.
摘要翻译：公开了一种接触FET器件的方法。该方法包括垂直凹陷器件隔离，其暴露源极和漏极两侧的侧壁表面。接下来，进行硅化，得到覆盖源极和漏极的顶表面和侧壁表面的硅化物层。接下来，以这样的方式施加金属触点，使得它们在其顶部和侧壁表面上接合硅化物层。还公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触件在其顶表面和其侧壁表面上接合硅化物。

3. 发明授权

US08324058B2 Contacts for FET devices 有权
标题翻译： FET器件的触点
公开(公告)号：US08324058B2
公开(公告)日：2012-12-04
申请号：US12941042
申请日：2010-11-06
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L21/336 , H01L21/76 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.
摘要翻译：公开了一种接触FET器件的方法。该方法包括垂直凹陷器件隔离，其暴露源极和漏极两侧的侧壁表面。接下来，进行硅化，得到覆盖源极和漏极的顶表面和侧壁表面的硅化物层。接下来，以这样的方式施加金属触点，使得它们在其顶部和侧壁表面上接合硅化物层。还公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触件在其顶表面和其侧壁表面上接合硅化物。

4. 发明申请

US20140024215A1 DOUBLE PATTERNING METHOD 有权
标题翻译：双重图案方法
公开(公告)号：US20140024215A1
公开(公告)日：2014-01-23
申请号：US13555306
申请日：2012-07-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
IPC分类号： B44C1/22 , H01B13/00 , H01L21/308
CPC分类号： H01L21/3086 , H01B13/00 , H01B19/04 , H01L21/0337 , H01L21/3081 , H01L21/32134 , H01L21/32137
摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
摘要翻译：公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

5. 发明授权

US08569868B2 Device having and method for forming fins with multiple widths 有权
标题翻译：具有用于形成多个宽度的翅片的装置和方法
公开(公告)号：US08569868B2
公开(公告)日：2013-10-29
申请号：US13552296
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
摘要翻译：公开了一种用于半导体器件的结构。该结构包括第一特征和第二特征。第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

6. 发明申请

US20130017667A1 SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130017667A1
公开(公告)日：2013-01-17
申请号：US13617464
申请日：2012-09-14
申请人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/28123 , H01L21/76224 , H01L21/84 , H01L27/11 , H01L27/1203
摘要： A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.
摘要翻译：半导体器件包括具有至少一个氮化物材料衬里隔离腔的衬底; 以及含有铪的电介质填充物，其至少部分地包含在并且至少部分地覆盖所述至少一个氮化物衬里隔离腔的至少一部分。

7. 发明申请

US20120292710A1 METHOD FOR SELF-ALIGNED METAL GATE CMOS 有权
标题翻译：自对准金属栅CMOS的方法
公开(公告)号：US20120292710A1
公开(公告)日：2012-11-22
申请号：US13108138
申请日：2011-05-16
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/092 , H01L21/3205
CPC分类号： H01L21/823842 , H01L29/66545 , H01L29/7833 , H01L29/7843 , H01L2924/13085 , H01L2924/13092
摘要： A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.
摘要翻译：半导体器件通过首先提供具有FET对前体的双栅极半导体器件结构形成，其包括nFET前体和pFET前体，其中nFET前体和pFET前体中的每一个包括伪栅极结构。至少一个保护层沉积在FET对前体之间，留下伪栅极结构。从nFET前体和pFET前体之一去除伪栅极结构，以在其中分别形成nFET栅极孔和pFET栅极孔中的一个。填充物沉积在形成的nFET栅极孔和pFET栅极之一中。

8. 发明申请

US20120280365A1 DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS 有权
标题翻译：具有形成具有多个宽度的FINS的装置和方法
公开(公告)号：US20120280365A1
公开(公告)日：2012-11-08
申请号：US13552296
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
摘要翻译：公开了一种用于半导体器件的结构。该结构包括第一特征和第二特征。第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

9. 发明申请

US20120223386A1 Asymmetric FinFET devices 有权
标题翻译：非对称FinFET器件
公开(公告)号：US20120223386A1
公开(公告)日：2012-09-06
申请号：US13470393
申请日：2012-05-14
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L21/2633 , H01L21/26506 , H01L21/26586 , H01L29/517 , H01L29/785 , H01L29/7855 , H01L29/7856
摘要： Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold- modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.
摘要翻译：公开了非对称FET器件，以及在翅片结构上制造这种非对称器件的方法。该制造方法包括在散热片上布置高k电介质层，随后是阈值修饰层，以倾斜角度进行离子轰击，该倾斜角度在翅片的侧面之一上除去阈值修饰层。完成的FET器件将是不对称的，因为阈值修饰层仅存在于翅片一侧的两个器件之一中。在替代实施例中，引入另外的不对称性，再次使用倾斜离子注入，导致用于翅片每侧上的两个FinFET器件的不同的栅极 - 导体材料。

10. 发明授权

US08242560B2 FinFET with thin gate dielectric layer 有权
标题翻译： FinFET具有薄栅介质层
公开(公告)号：US08242560B2
公开(公告)日：2012-08-14
申请号：US12688347
申请日：2010-01-15
申请人： Eduard A. Cartier , Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Eduard A. Cartier , Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/66795
摘要： A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.
摘要翻译：提供了一种半导体器件，其在一个实施例中包括在电介质表面之上的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区，漏区存在于半导体鳍结构的相对端。具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。至少一个栅极导体层与高k栅极电介质层直接接触。还提供了一种形成上述装置的方法。

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