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1. 发明申请

US20120306015A1 CONTACTS FOR FET DEVICES 审中-公开
标题翻译： FET器件的接触
公开(公告)号：US20120306015A1
公开(公告)日：2012-12-06
申请号：US13562355
申请日：2012-07-31
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A device characterized as being an FET device structure with enlarged contact areas is disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide layer on its top surface and on its sidewall surface.
摘要翻译：公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触物接合在其顶表面及其侧壁表面上的硅化物层。

2. 发明申请

US20120112279A1 CONTACTS FOR FET DEVICES 有权
标题翻译： FET器件的接触
公开(公告)号：US20120112279A1
公开(公告)日：2012-05-10
申请号：US12941042
申请日：2010-11-06
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L29/772 , H01L29/45 , H01L21/28
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.
摘要翻译：公开了一种接触FET器件的方法。该方法包括垂直凹陷器件隔离，其暴露源极和漏极两侧的侧壁表面。接下来，进行硅化，得到覆盖源极和漏极的顶表面和侧壁表面的硅化物层。接下来，以这样的方式施加金属触点，使得它们在其顶部和侧壁表面上接合硅化物层。还公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触件在其顶表面和其侧壁表面上接合硅化物。

3. 发明授权

US08324058B2 Contacts for FET devices 有权
标题翻译： FET器件的触点
公开(公告)号：US08324058B2
公开(公告)日：2012-12-04
申请号：US12941042
申请日：2010-11-06
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L21/336 , H01L21/76 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.
摘要翻译：公开了一种接触FET器件的方法。该方法包括垂直凹陷器件隔离，其暴露源极和漏极两侧的侧壁表面。接下来，进行硅化，得到覆盖源极和漏极的顶表面和侧壁表面的硅化物层。接下来，以这样的方式施加金属触点，使得它们在其顶部和侧壁表面上接合硅化物层。还公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触件在其顶表面和其侧壁表面上接合硅化物。

4. 发明申请

US20120267685A1 METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe 有权
标题翻译：具有PFET通道SiGe的金属栅极和高K介质器件
公开(公告)号：US20120267685A1
公开(公告)日：2012-10-25
申请号：US13539700
申请日：2012-07-02
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.
摘要翻译：在电路结构中，PFET器件具有栅极电介质，其包括高k电介质，具有金属的栅格，p源极/漏极和形成在p源极/漏极上的硅化物层; NFET器件包括栅极电介质，其包括高k电介质，具有金属的盖板，在n源极/漏极上形成的n源极/漏极和硅化物层。外延SiGe存在于PFET栅极电介质的下面并与PFET栅极电介质直接接触，而外延SiGe不存在于NFET栅极电介质下方。

5. 发明申请

US20110068369A1 METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe 有权
标题翻译：具有PFET通道SiGe的金属栅极和高K介质器件
公开(公告)号：US20110068369A1
公开(公告)日：2011-03-24
申请号：US12563032
申请日：2009-09-18
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： A method for fabricating a circuit structure is disclosed. The method includes depositing epitaxially a SiGe layer onto both NFET and PFET portions of a Si surface. Blanket disposing a first sequence of layers over the SiGe layer, including a high-k dielectric and a metal, and incorporating this first sequence of layers into the gatestacks and gate insulators of both NFET devices and PFET devices. This first sequence of layers is selected to yield desired device parameter values for the PFET devices. The method further includes removing the gatestack, the gate dielectric, and the SiGe layer, and re-forming the NFET devices by deploying a second sequence of layers that include a second high-k dielectric and a second metal. The second sequence of layers is selected to yield desired device parameter values for the NFET devices. A circuit structure is also disclosed. PFET devices have a gate dielectric with a high-k dielectric, a gatestack with a metal, and a silicide formed over the p-source/drain. NFET devices also include a gate dielectric with a high-k dielectric, a gatestack with a metal, and silicide formed over the n-source/drain. An epitaxial SiGe layer over the substrate surface is present everywhere in the device structures with the exception that it is absent underneath the NFET gate dielectric. The PFET and NFET device parameters are independently optimized through the composition of their gate dielectrics and gate stacks.
摘要翻译：公开了一种制造电路结构的方法。该方法包括将SiGe层外延沉积到Si表面的NFET和PFET部分上。毯子在SiGe层上设置第一层次序列，包括高k电介质和金属，并将该第一层序列并入到两个NFET器件和PFET器件的绝缘体和栅极绝缘体中。选择该第一层次序列以产生PFET器件的期望的器件参数值。该方法还包括去除盖板，栅极电介质和SiGe层，以及通过布置包括第二高k电介质和第二金属的第二层序列来重新形成NFET器件。选择第二层次序列以产生NFET器件的期望的器件参数值。还公开了电路结构。 PFET器件具有具有高k电介质的栅极电介质，具有金属的栅极电极和形成在p源极/漏极上的硅化物。 NFET器件还包括具有高k电介质的栅极电介质，具有金属的Gatestack以及形成在n源极/漏极上的硅化物。在衬底表面上的外延SiGe层存在于器件结构中的任何地方，不同的是它不在NFET栅极电介质的下方。 PFET和NFET器件参数通过其栅极电介质和栅极叠层的组成独立优化。

6. 发明申请

US20120322251A1 Borderless Contacts For Semiconductor Devices 有权
标题翻译：半导体器件无边界接触
公开(公告)号：US20120322251A1
公开(公告)日：2012-12-20
申请号：US13597331
申请日：2012-08-29
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L21/28
CPC分类号： H01L29/42364 , H01L21/76831 , H01L21/76897 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material.
摘要翻译：在本发明的一个示例性实施例中，一种方法（例如，制造具有无边界接触的半导体器件）包括：在衬底上形成第一栅极结构; 在所述第一栅极结构上沉积层间电介质; 平面化所述层间电介质以暴露所述第一栅极结构的顶表面; 去除所述第一栅极结构的至少一部分; 形成第二栅极结构来代替第一栅极结构; 通过去除所述层间电介质的一部分来形成所述无边界接触的接触区域; 以及通过用含金属材料填充接触区域来形成无边界接触。

7. 发明授权

US09276079B2 Semiconductor device exhibiting reduced parasitics and method for making same 有权
公开(公告)号：US09276079B2
公开(公告)日：2016-03-01
申请号：US13617575
申请日：2012-09-14
申请人： Bruce B. Doris , Kangguo Cheng , Keith Kwong Hon-Wong
发明人： Bruce B. Doris , Kangguo Cheng , Keith Kwong Hon-Wong
IPC分类号： H01L21/31 , H01L29/51
CPC分类号： H01L29/518 , H01L27/24 , H01L29/41775 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.

8. 发明授权

US08796773B2 Metal gate and high-K dielectric devices with PFET channel SiGe 有权
标题翻译：具有PFET通道SiGe的金属栅极和高K电介质器件
公开(公告)号：US08796773B2
公开(公告)日：2014-08-05
申请号：US13539700
申请日：2012-07-02
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L27/12
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.
摘要翻译：在电路结构中，PFET器件具有栅极电介质，其包括高k电介质，具有金属的栅格，p源极/漏极和形成在p源极/漏极上的硅化物层; NFET器件包括包括高k电介质的栅极电介质，具有金属的糖饼，在n源极/漏极上形成的n源极/漏极和硅化物层。外延SiGe存在于PFET栅极电介质的下面并与PFET栅极电介质直接接触，而外延SiGe不存在于NFET栅极电介质下方。

9. 发明授权

US08298882B2 Metal gate and high-K dielectric devices with PFET channel SiGe 有权
标题翻译：具有PFET通道SiGe的金属栅极和高K电介质器件
公开(公告)号：US08298882B2
公开(公告)日：2012-10-30
申请号：US12563032
申请日：2009-09-18
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： Fabricating of semiconductor devices includes: depositing epitaxially a SiGe layer onto both NFET and PFET portions of a Si surface; blanket disposing a first sequence of layers over the SiGe layer including a high-k dielectric and a metal, incorporating the first sequence of layers into the gatestacks and gate insulators of both NFET devices and PFET devices; the first sequence of layers is selected to yield desired device parameter values for the PFET devices; removing the gatestack, the gate dielectric, and the SiGe layer for the NFET devices, re-forming the NFET devices by deploying a second sequence of layers that include a second high-k dielectric and a second metal; the second sequence of layers is selected to yield desired device parameter values for the NFET devices.
摘要翻译：半导体器件的制造包括：在Si表面的NFET和PFET部分上外延沉积SiGe层; 在包括高k电介质和金属的SiGe层上布置第一层序列，将第一层序列结合到两个NFET器件和PFET器件的栅极绝缘体和栅极绝缘体中; 选择层的第一序列以产生PFET器件的期望的器件参数值; 去除用于NFET器件的盖板，栅极电介质和SiGe层，通过布置包括第二高k电介质和第二金属的第二层序列来重新形成NFET器件; 选择第二层次序列以产生NFET器件的期望的器件参数值。

10. 发明申请

US20120256277A1 SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME 有权
标题翻译：半导体器件展示减少的PARASITICS及其制造方法
公开(公告)号：US20120256277A1
公开(公告)日：2012-10-11
申请号：US13083893
申请日：2011-04-11
申请人： Bruce B. Doris , Kangguo Cheng , Keith Kwong Hon Wong
发明人： Bruce B. Doris , Kangguo Cheng , Keith Kwong Hon Wong
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/518 , H01L27/24 , H01L29/41775 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.
摘要翻译：半导体器件包括衬底和设置在衬底上的栅极堆叠。栅极堆叠的上层是金属栅极导体，栅极叠层的下层是栅极电介质。栅极触点与金属栅极导体直接接触。

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