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1. 发明授权

US09012321B1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09012321B1
公开(公告)日：2015-04-21
申请号：US14283666
申请日：2014-05-21
申请人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Nak-jin Son , Ji-young Kim
发明人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Nak-jin Son , Ji-young Kim
IPC分类号： H01L21/00 , H01L21/762 , H01L21/768
CPC分类号： H01L21/76224 , H01L21/743 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成牺牲膜作为形成半导体器件的工艺的一部分。牺牲膜相对于半导体器件的其它材料具有相对高的蚀刻选择性，以便减少蚀刻掩模的损耗并提高半导体器件的部件（例如，埋入触点）的质量。

2. 发明申请

US20150132942A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING BURIED CONTACTS AND RELATED SEMICONDUCTOR DEVICES 有权
标题翻译：制造带有接触触点的半导体器件和相关半导体器件的方法
公开(公告)号：US20150132942A1
公开(公告)日：2015-05-14
申请号：US14538832
申请日：2014-11-12
申请人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Ji-young Kim
发明人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Ji-young Kim
IPC分类号： H01L21/768 , H01L21/321 , H01L21/3205 , H01L21/311
CPC分类号： H01L27/10823 , H01L21/31111 , H01L21/31144 , H01L21/76224 , H01L23/5226 , H01L23/528 , H01L23/53295 , H01L27/10814 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10891
摘要： Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：通过在第一方向上布置的第一槽形成位线结构，该第一槽在第一方向上延伸，并且在垂直于第一方向的第二方向上彼此间隔开，在其中掩埋有字线的衬底上; 在位线结构的两个侧壁上形成多层间隔物; 形成牺牲层以填充第一凹槽; 通过图案化牺牲层形成在第一方向和第二方向上彼此间隔开的第二凹槽; 蚀刻位于第二凹槽中的多层间隔物的最外层间隔; 在第二槽中形成第一辅助间隔件; 形成绝缘层以填充第二凹槽; 以及通过去除牺牲层和绝缘层，在第一辅助隔离物的两侧上，在第一方向和第二方向上形成彼此间隔开的第三槽。

3. 发明授权

US09419000B2 Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices 有权
标题翻译：制造具有掩埋触点和相关半导体器件的半导体器件的方法
公开(公告)号：US09419000B2
公开(公告)日：2016-08-16
申请号：US14538832
申请日：2014-11-12
申请人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Ji-young Kim
发明人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Ji-young Kim
IPC分类号： H01L21/768 , H01L27/108
CPC分类号： H01L27/10823 , H01L21/31111 , H01L21/31144 , H01L21/76224 , H01L23/5226 , H01L23/528 , H01L23/53295 , H01L27/10814 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10891
摘要： Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：通过在第一方向上布置的第一槽形成位线结构，该第一槽在第一方向上延伸，并且在垂直于第一方向的第二方向上彼此间隔开，在其中掩埋有字线的衬底上; 在位线结构的两个侧壁上形成多层间隔物; 形成牺牲层以填充第一凹槽; 通过图案化牺牲层形成在第一方向和第二方向上彼此间隔开的第二凹槽; 蚀刻位于第二凹槽中的多层间隔物的最外层间隔; 在第二槽中形成第一辅助间隔件; 形成绝缘层以填充第二凹槽; 以及通过去除牺牲层和绝缘层，在第一辅助隔离物的两侧上，在第一方向和第二方向上形成彼此间隔开的第三槽。

4. 发明授权

US08362536B2 Semiconductor device having vertical channel transistor and methods of fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08362536B2
公开(公告)日：2013-01-29
申请号：US12904344
申请日：2010-10-14
申请人： Hyung-woo Chung , Yong-chul Oh , Yoo-sang Hwang , Gyo-young Jin , Hyeong-sun Hong , Dae-ik Kim
发明人： Hyung-woo Chung , Yong-chul Oh , Yoo-sang Hwang , Gyo-young Jin , Hyeong-sun Hong , Dae-ik Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10805 , H01L27/0207 , H01L27/10876 , H01L27/10885
摘要： A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.
摘要翻译：半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上，所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。

5. 发明申请

US20120094454A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR 有权
标题翻译：制造包括垂直通道晶体管的半导体器件的方法
公开(公告)号：US20120094454A1
公开(公告)日：2012-04-19
申请号：US13240135
申请日：2011-09-22
申请人： Young-seung Cho , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
发明人： Young-seung Cho , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
IPC分类号： H01L21/336 , H01L21/302
CPC分类号： H01L29/7827 , H01L27/0207 , H01L27/10873 , H01L27/10885 , H01L29/66666
摘要： A method of fabricating a semiconductor device including a vertical channel transistor. The method may include: forming a plurality of first device isolation layers in a substrate as a pattern of lines having a first depth from an upper surface of a substrate, to define a plurality of active regions, forming a plurality of trenches having a second depth smaller than the first depth, etching portions of the substrate that are under some of the plurality of trenches that are selected at a predetermined interval, to form a plurality of device isolation trenches having a third depth that is greater than the second depth, forming second device isolation layers that include an insulating material, in lower portions of the plurality of device isolation trenches, and forming buried bit lines in lower portions of the plurality of trenches and the plurality of device isolation trenches.
摘要翻译：一种制造包括垂直沟道晶体管的半导体器件的方法。该方法可以包括：在衬底中形成多个第一器件隔离层作为具有从衬底的上表面的第一深度的线的图案，以限定多个有源区，形成具有第二深度的多个沟槽小于第一深度，蚀刻在以预定间隔选择的多个沟槽中的一些下方的衬底的部分，以形成具有大于第二深度的第三深度的多个器件隔离沟槽，形成第二深度在所述多个器件隔离沟槽的下部包括绝缘材料的器件隔离层，以及在所述多个沟槽的下部和所述多个器件隔离沟槽中形成掩埋位线。

6. 发明授权

US08420485B2 Semiconductor device having vertical channel transistor and method of manufacturing the same 有权
标题翻译：具有垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08420485B2
公开(公告)日：2013-04-16
申请号：US13243174
申请日：2011-09-23
申请人： Young-seung Cho , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
发明人： Young-seung Cho , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L29/66666
摘要： A semiconductor device and method of manufacturing the same. The method includes: defining a first active area and a second active area on a substrate, the first and second active areas being in a line form, forming a first main trench and a second main trench on the substrate, forming a first sub-trench and a second sub-trench in bottoms of the first and second main trenches, respectively, forming a buried insulation layer filling the first and second sub-trenches, partially exposing the substrate at an area where the first active area crosses with the first sub-trench and an area where the second active area crosses with the second sub-trench and forming the first buried bit line and the second buried bit line on the buried insulation layer, and the first and second buried bit lines being extended in parallel to each other.
摘要翻译：一种半导体器件及其制造方法。该方法包括：在衬底上限定第一有源区和第二有源区，第一和第二有源区为线形，在衬底上形成第一主沟槽和第二主沟槽，形成第一子沟槽以及分别在所述第一和第二主沟槽的底部中的第二子沟槽，形成填充所述第一和第二子沟槽的掩埋绝缘层，在所述第一有源区域与所述第一子沟槽交叉的区域部分地暴露所述衬底，沟槽和第二有源区域与第二子沟槽交叉的区域，并且在掩埋绝缘层上形成第一掩埋位线和第二掩埋位线，并且第一和第二掩埋位线彼此平行地延伸。

7. 发明申请

US20120094455A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体器件及其制造方法
公开(公告)号：US20120094455A1
公开(公告)日：2012-04-19
申请号：US13243174
申请日：2011-09-23
申请人： Young-seung CHO , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
发明人： Young-seung CHO , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L29/66666
摘要： A semiconductor device and method of manufacturing the same. The method includes: defining a first active area and a second active area on a substrate, the first and second active areas being in a line form, forming a first main trench and a second main trench on the substrate, forming a first sub-trench and a second sub-trench in bottoms of the first and second main trenches, respectively, forming a buried insulation layer filling the first and second sub-trenches, partially exposing the substrate at an area where the first active area crosses with the first sub-trench and an area where the second active area crosses with the second sub-trench and forming the first buried bit line and the second buried bit line on the buried insulation layer, and the first and second buried bit lines being extended in parallel to each other.
摘要翻译：一种半导体器件及其制造方法。该方法包括：在衬底上限定第一有源区和第二有源区，第一和第二有源区为线形，在衬底上形成第一主沟槽和第二主沟槽，形成第一子沟槽以及分别在所述第一和第二主沟槽的底部中的第二子沟槽，形成填充所述第一和第二子沟槽的掩埋绝缘层，在所述第一有源区域与所述第一子沟槽交叉的区域部分地暴露所述衬底，沟槽和第二有源区域与第二子沟槽交叉的区域，并且在掩埋绝缘层上形成第一掩埋位线和第二掩埋位线，并且第一和第二掩埋位线彼此平行地延伸。

8. 发明授权

US08497174B2 Method of fabricating semiconductor device including vertical channel transistor 有权
标题翻译：制造包括垂直沟道晶体管的半导体器件的方法
公开(公告)号：US08497174B2
公开(公告)日：2013-07-30
申请号：US13240135
申请日：2011-09-22
申请人： Young-seung Cho , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
发明人： Young-seung Cho , Dae-ik Kim , Yoo-sang Hwang , Hyun-woo Chung
IPC分类号： H01L21/336 , H01L21/76 , H01L21/4763
CPC分类号： H01L29/7827 , H01L27/0207 , H01L27/10873 , H01L27/10885 , H01L29/66666
摘要： A method of fabricating a semiconductor device including a vertical channel transistor. The method may include: forming a plurality of first device isolation layers in a substrate as a pattern of lines having a first depth from an upper surface of a substrate, to define a plurality of active regions, forming a plurality of trenches having a second depth smaller than the first depth, etching portions of the substrate that are under some of the plurality of trenches that are selected at a predetermined interval, to form a plurality of device isolation trenches having a third depth that is greater than the second depth, forming second device isolation layers that include an insulating material, in lower portions of the plurality of device isolation trenches, and forming buried bit lines in lower portions of the plurality of trenches and the plurality of device isolation trenches.
摘要翻译：一种制造包括垂直沟道晶体管的半导体器件的方法。该方法可以包括：在衬底中形成多个第一器件隔离层作为具有从衬底的上表面的第一深度的线的图案，以限定多个有源区，形成具有第二深度的多个沟槽小于第一深度，蚀刻在以预定间隔选择的多个沟槽中的一些下方的衬底的部分，以形成具有大于第二深度的第三深度的多个器件隔离沟槽，形成第二深度在所述多个器件隔离沟槽的下部包括绝缘材料的器件隔离层，以及在所述多个沟槽的下部和所述多个器件隔离沟槽中形成掩埋位线。

9. 发明授权

US08492832B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08492832B2
公开(公告)日：2013-07-23
申请号：US13571805
申请日：2012-08-10
申请人： Ji-young Kim , Gyo-young Jin , Hyeong-sun Hong , Yoo-sang Hwang , Sung-kwan Choi , Hyun-woo Chung
发明人： Ji-young Kim , Gyo-young Jin , Hyeong-sun Hong , Yoo-sang Hwang , Sung-kwan Choi , Hyun-woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , H01L27/10823 , H01L29/4236
摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.
摘要翻译：半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

10. 发明申请

US20130037882A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130037882A1
公开(公告)日：2013-02-14
申请号：US13571805
申请日：2012-08-10
申请人： Ji-young Kim , Gyo-young Jin , Hyeong-sun Hong , Yoo-sang Hwang , Sung-kwan Choi , Hyun-woo Chung
发明人： Ji-young Kim , Gyo-young Jin , Hyeong-sun Hong , Yoo-sang Hwang , Sung-kwan Choi , Hyun-woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , H01L27/10823 , H01L29/4236
摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.
摘要翻译：半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

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