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1. 发明申请

US20100318313A1 MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES 失效
标题翻译：统计应力的测量方法和阵列结构和可靠性结构测试
公开(公告)号：US20100318313A1
公开(公告)日：2010-12-16
申请号：US12482999
申请日：2009-06-11
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译：在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛。在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。

2. 发明授权

US08120356B2 Measurement methodology and array structure for statistical stress and test of reliabilty structures 失效
标题翻译：统计应力的测量方法和阵列结构以及可靠性结构的测试
公开(公告)号：US08120356B2
公开(公告)日：2012-02-21
申请号：US12482999
申请日：2009-06-11
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
IPC分类号： G01V3/00
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译：在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛。在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。

3. 发明授权

US07868640B2 Array-based early threshold voltage recovery characterization measurement 失效
标题翻译：基于阵列的早期阈值电压恢复特性测量
公开(公告)号：US07868640B2
公开(公告)日：2011-01-11
申请号：US12061077
申请日：2008-04-02
申请人： Kanak B Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
发明人： Kanak B Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译：一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。

4. 发明申请

US20090251167A1 Array-Based Early Threshold Voltage Recovery Characterization Measurement 失效
标题翻译：基于阵列的早期阈值电压恢复特性测量
公开(公告)号：US20090251167A1
公开(公告)日：2009-10-08
申请号：US12061077
申请日：2008-04-02
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译：一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。

5. 发明授权

US08217671B2 Parallel array architecture for constant current electro-migration stress testing 失效
标题翻译：用于恒流电迁移应力测试的并行阵列架构
公开(公告)号：US08217671B2
公开(公告)日：2012-07-10
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/00
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译：提供了一种用于恒流电迁移应力测试的并行阵列架构。并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分电流源逻辑。使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

6. 发明申请

US20100327892A1 Parallel Array Architecture for Constant Current Electro-Migration Stress Testing 失效
标题翻译：用于恒流电迁移应力测试的并行阵列架构
公开(公告)号：US20100327892A1
公开(公告)日：2010-12-30
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译：提供了一种用于恒流电迁移应力测试的并行阵列架构。并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分电流源逻辑。使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

7. 发明授权

US08178434B2 On-chip embedded thermal antenna for chip cooling 有权
标题翻译：片上嵌入式热天线芯片散热
公开(公告)号：US08178434B2
公开(公告)日：2012-05-15
申请号：US13244998
申请日：2011-09-26
申请人： Fen Chen , Jeffrey P. Gambino , Alvin W. Strong
发明人： Fen Chen , Jeffrey P. Gambino , Alvin W. Strong
IPC分类号： H01L21/768
CPC分类号： H01L23/585 , H01L23/3677 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.
摘要翻译：一种装置包括半导体芯片内的第一层，其具有与其它有源结构电连接并且具有电隔离的第一无效结构的有源结构。半导体芯片内的第二层物理连接到第一层。第二层包括绝缘体并具有第二非活性结构。第一非活性结构与第二非活性结构物理对准。

8. 发明申请

US20120015511A1 ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING 有权
标题翻译：芯片嵌入式热天线芯片冷却
公开(公告)号：US20120015511A1
公开(公告)日：2012-01-19
申请号：US13244998
申请日：2011-09-26
申请人： FEN CHEN , Jeffrey P. Gambino , Alvin W. Strong
发明人： FEN CHEN , Jeffrey P. Gambino , Alvin W. Strong
IPC分类号： H01L21/768
CPC分类号： H01L23/585 , H01L23/3677 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.
摘要翻译：一种装置包括半导体芯片内的第一层，其具有与其它有源结构电连接并且具有电隔离的第一无效结构的有源结构。半导体芯片内的第二层物理连接到第一层。第二层包括绝缘体并具有第二非活性结构。第一非活性结构与第二非活性结构物理对准。

9. 发明申请

US20080237797A1 ELECTRICALLY TUNABLE RESISTOR AND RELATED METHODS 失效
标题翻译：电气可控电阻及相关方法
公开(公告)号：US20080237797A1
公开(公告)日：2008-10-02
申请号：US11691755
申请日：2007-03-27
申请人： ICKO E.T. IBEN , Alvin W. Strong
发明人： ICKO E.T. IBEN , Alvin W. Strong
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01C17/267 , H01C7/006 , H01L27/016 , H01L27/0802
摘要： An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor.
摘要翻译：公开了一种电可调电阻器及相关方法。在一个实施例中，电阻器包括第一电阻层，至少一个第二电阻层，以及第一电阻层和至少一个第二电阻层的中间相互扩散层。一种方法可以包括提供由至少一个绝缘层包围的不同材料的第一多个层，并且使电流脉冲通过第一多个层以影响第一多个层的导电结构，以获得第一预定的电阻的电阻值。

10. 发明授权

US06891359B2 Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效
标题翻译：电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性
公开(公告)号：US06891359B2
公开(公告)日：2005-05-10
申请号：US10248506
申请日：2003-01-24
申请人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
发明人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
IPC分类号： G01N27/00 , G01R27/00 , G01R31/02 , G01R31/28
CPC分类号： G01R31/2855
摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.
摘要翻译：一种用于预测门可靠性的方法和系统。该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分故障，确定第一个失败和第二个失败之间的关系，并且n ^{th 失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。这种关系可以量化。}

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