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1. 发明授权

US07868640B2 Array-based early threshold voltage recovery characterization measurement 失效
标题翻译：基于阵列的早期阈值电压恢复特性测量
公开(公告)号：US07868640B2
公开(公告)日：2011-01-11
申请号：US12061077
申请日：2008-04-02
申请人： Kanak B Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
发明人： Kanak B Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译：一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。

2. 发明申请

US20090251167A1 Array-Based Early Threshold Voltage Recovery Characterization Measurement 失效
标题翻译：基于阵列的早期阈值电压恢复特性测量
公开(公告)号：US20090251167A1
公开(公告)日：2009-10-08
申请号：US12061077
申请日：2008-04-02
申请人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John Greg Massey , Alvin W. Strong
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译：一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。

3. 发明授权

US07375371B2 Structure and method for thermally stressing or testing a semiconductor device 有权
标题翻译：用于热应力或测试半导体器件的结构和方法
公开(公告)号：US07375371B2
公开(公告)日：2008-05-20
申请号：US11307324
申请日：2006-02-01
申请人： Giuseppe La Rosa , Kevin W. Kolvenbach , John Greg Massey , Ping-Chuan Wang , Kai Xiu
发明人： Giuseppe La Rosa , Kevin W. Kolvenbach , John Greg Massey , Ping-Chuan Wang , Kai Xiu
IPC分类号： H01L23/58 , H01L29/10 , G01R31/02
CPC分类号： G01R31/2856
摘要： A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.
摘要翻译：提供了一种在衬底的连续有源半导体区域中包括至少一个半导体器件和扩散加热器的结构。一个或多个半导体器件设置在有源半导体区域的第一区域中，并且扩散加热器邻近设置，其主要由包含在有源半导体区域中的半导体材料组成。通过使用分离栅极实现第一区域和扩散加热器之间的导电隔离。分离栅极覆盖在第一区域和扩散加热器之间的有源半导体区域的中间区域，并且分离栅极可偏置以将第一区域与扩散加热器导电隔离。

4. 发明申请

US20120259575A1 INTEGRATED CIRCUIT CHIP INCORPORATING A TEST CIRCUIT THAT ALLOWS FOR ON-CHIP STRESS TESTING IN ORDER TO MODEL OR MONITOR DEVICE PERFORMANCE DEGRADATION 审中-公开
标题翻译：集成电路芯片，包含允许在模型或监视器件性能下降的片上应力测试的测试电路
公开(公告)号：US20120259575A1
公开(公告)日：2012-10-11
申请号：US13082066
申请日：2011-04-07
申请人： Carole D. Graas , Deborah M. Massey , John Greg Massey , Pascal A. Nsame
发明人： Carole D. Graas , Deborah M. Massey , John Greg Massey , Pascal A. Nsame
IPC分类号： G06F19/00
CPC分类号： G01R31/30 , G01R31/3187
摘要： Disclosed is an integrated circuit chip incorporating a test circuit having multiple logic blocks. Each logic block is a matrix of individually selectable, physically different, test devices in a specific class of devices. An embedded processor ensures that specific stress conditions are selectively applied to the test devices and further controls selective testing, by a sensor system, of the test devices to determine the impact of the applied stress conditions. In a laboratory or test system environment, accelerated stress conditions are selectively applied to the test devices and the testing results are used to model device performance degradation due to class-specific failure mechanisms. In the field, stress conditions are selectively applied to test devices so as to mimic stress conditions impacting active devices in use on the same chip and the testing results are used to indirectly monitor performance degradation of the active devices due to class-specific failure mechanisms.
摘要翻译：公开了一种集成了具有多个逻辑块的测试电路的集成电路芯片。每个逻辑块是特定类别设备中可单独选择的，物理上不同的测试设备的矩阵。嵌入式处理器确保特定的应力条件被选择性地应用于测试装置，并进一步控制传感器系统对测试装置的选择性测试，以确定施加的应力条件的影响。在实验室或测试系统环境中，加速的应力条件被选择性地应用于测试设备，并且测试结果被用于由于特定于类别的故障机制而对设备性能的劣化进行建模。在现场，应力条件选择性地应用于测试装置，以便模拟影响同一芯片上使用中的有源器件的应力状况，并且测试结果用于间接地监视由于类特定故障机制而导致的有源器件的性能下降。

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