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1. 发明授权

US5835402A Non-volatile storage for standard CMOS integrated circuits 失效
标题翻译：标准CMOS集成电路的非易失性存储
公开(公告)号：US5835402A
公开(公告)日：1998-11-10
申请号：US825236
申请日：1997-03-27
申请人： Kameswara K. Rao , Martin L. Voogel
发明人： Kameswara K. Rao , Martin L. Voogel
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , G11C16/30 , G11C17/16 , G11C17/18 , G11C7/00
CPC分类号： G11C17/18 , G11C16/0441 , G11C16/10 , G11C16/26 , G11C16/30 , G11C17/16
摘要： Non-volatile storage elements are provided on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are either one-time programmable devices which are programmed by rupturing their gate oxide, EEPROM floating gate transistor cells, or other EEPROM cells.
摘要翻译：非易失性存储元件设置在集成电路上，其中非易失性存储元件是低电压CMOS器件，因此在制造意义上与集成电路上的其它类似晶体管兼容，从而不需要用于非集成电路的特殊类型的晶体管非易失存储。非易失性存储元件是通过破坏其栅极氧化物，EEPROM浮栅晶体管单元或其它EEPROM单元来编程的一次性可编程器件。

2. 发明授权

US6055205A Decoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process 有权
标题翻译：解码器用于在标准sub 0.35微米CMOS工艺中使用栅极击穿结构的非易失性存储器阵列
公开(公告)号：US6055205A
公开(公告)日：2000-04-25
申请号：US262981
申请日：1999-03-05
申请人： Kameswara K. Rao , Martin L. Voogel
发明人： Kameswara K. Rao , Martin L. Voogel
IPC分类号： G11C16/08 , G11C8/00
CPC分类号： G11C16/08
摘要： A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process. The state of the low voltage storage transistor can be read through the p-channel transistor, or through a dedicated high voltage n-channel transistor. In one embodiment, the programming voltage is generated by a charge pump circuit fabricated in accordance with a standard sub 0.35 micron process. In another embodiment, the decoder circuits that access the non-volatile memory cell use high voltage p-channel transistors to transmit the high programming voltage. Another embodiment of the present invention includes a system-on-a-chip structure that implements the non-volatile memory of the present invention.
摘要翻译：提供了一种非易失性存储单元，其包括具有共同连接到地的源极区和漏极区的低电压CMOS存储晶体管。通过向其栅极施加高编程电压来编程低电压存储晶体管，从而破坏存储晶体管的栅极氧化物。高编程电压通过高压p沟道晶体管施加到低电压存储晶体管。高压p沟道晶体管具有比存储晶体管更厚的栅极氧化物，从而使得p沟道晶体管能够承受更高的电压。高压p沟道晶体管也具有比相同尺寸的高电压n沟道晶体管更高的击穿电压。低电压存储晶体管和高压p沟道晶体管都按照标准的次级0.35微米工艺制造。低电压存储晶体管的状态可以通过p沟道晶体管或通过专用高压n沟道晶体管来读取。在一个实施例中，编程电压由根据标准次级0.35微米工艺制造的电荷泵电路产生。在另一个实施例中，访问非易失性存储单元的解码器电路使用高电压p沟道晶体管来传输高编程电压。本发明的另一实施例包括实现本发明的非易失性存储器的片上系统结构。

3. 发明授权

US06438065B1 Redundancy architecture and method for non-volatile storage 有权
标题翻译：用于非易失性存储的冗余架构和方法
公开(公告)号：US06438065B1
公开(公告)日：2002-08-20
申请号：US09552280
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , Michael J. Hart
发明人： Kameswara K. Rao , Martin L. Voogel , Michael J. Hart
IPC分类号： G11C800
CPC分类号： G11C16/08
摘要： A field programmable gate array (FPGA) includes a first non-volatile memory cell and a second non-volatile memory cell. Each of the two non-volatile memory cells is capable of storing at least one bit of information. The second non-volatile memory cell provides redundant storage of the information stored in the first non-volatile memory cell. A read circuit is coupled to the first non-volatile memory cell and the second non-volatile memory cell. The read circuit simultaneously reads the information stored in the first and second non-volatile memory cells, The read circuit reads the information stored in the first non-volatile memory cell even if the second non-volatile memory cell is defective or is not programmed properly. The FPGA may include a third non-volatile memory cell coupled to the read circuit, which provides redundant storage of the information stored in the first non-volatile memory cell. Each non-volatile memory cell includes a storage transistor having a source and a drain, both of which are coupled to ground. Additionally, each storage transistor has a gate oxide. Each non-volatile memory cell is programmed by breaking the gate oxide of the storage transistor.
摘要翻译：现场可编程门阵列（FPGA）包括第一非易失性存储单元和第二非易失性存储单元。两个非易失性存储器单元中的每一个能够存储至少一个位的信息。第二非易失性存储单元提供存储在第一非易失性存储单元中的信息的冗余存储。读取电路耦合到第一非易失性存储单元和第二非易失性存储单元。读取电路同时读取存储在第一和第二非易失性存储单元中的信息。即使第二非易失性存储器单元有缺陷或未正确编程，读取电路读取存储在第一非易失性存储器单元中的信息。 FPGA可以包括耦合到读取电路的第三非易失性存储器单元，其提供存储在第一非易失性存储器单元中的信息的冗余存储。每个非易失性存储单元包括具有源极和漏极的存储晶体管，二者都耦合到地。另外，每个存储晶体管具有栅极氧化物。通过断开存储晶体管的栅极氧化物来对每个非易失性存储单元进行编程。

4. 发明授权

US06243294B1 Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process 有权
标题翻译：用于非易失性存储的内存架构，使用标准次级0.35微米工艺中的栅极击穿结构
公开(公告)号：US06243294B1
公开(公告)日：2001-06-05
申请号：US09552625
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , Michael J. Hart
发明人： Kameswara K. Rao , Martin L. Voogel , Michael J. Hart
IPC分类号： G11C1604
CPC分类号： G11C16/08
摘要： A field programmable gate array (FPGA) contains an array of memory cells. A word line is coupled to a row of memory cells in the array. A second signal line is coupled to the row of memory cells and extends in parallel with the word line. The second signal line applies a zero voltage to the memory cells when programming a memory cell in the row of memory cells. The second signal line applies a positive voltage to the memory cells when programming a memory cell outside the row of memory cells. Each memory cell is a one-time programmable non-volatile memory cell. Each memory cell includes a storage transistor and an access transistor coupled to one another. The memory cell can be programmed by selecting a word line and a bit line associated with the memory cell being programmed. A zero voltage is applied to a third signal line coupled to the memory cell and extending parallel to the word line. A programming voltage is applied to the selected bit line to program the memory cell.
摘要翻译：现场可编程门阵列（FPGA）包含存储单元阵列。字线耦合到阵列中的一行存储器单元。第二信号线耦合到该行存储器单元并且与字线并行延伸。当对存储器单元行中的存储单元进行编程时，第二信号线向存储器单元施加零电压。当对存储器单元行之外的存储单元进行编程时，第二信号线向存储器单元施加正电压。每个存储单元是一次性可编程非易失性存储单元。每个存储单元包括彼此耦合的存储晶体管和存取晶体管。可以通过选择与被编程的存储器单元相关联的字线和位线来对存储器单元进行编程。零电压被施加到耦合到存储器单元并平行于字线延伸的第三信号线。将编程电压施加到所选位线以对存储器单元进行编程。

5. 发明授权

US06208549B1 One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS 有权
标题翻译：一次性可编程多熔丝电路，用于在标准子0.35微米CMOS中实现非易失性功能
公开(公告)号：US06208549B1
公开(公告)日：2001-03-27
申请号：US09513235
申请日：2000-02-24
申请人： Kameswara K. Rao , Martin L. Voogel
发明人： Kameswara K. Rao , Martin L. Voogel
IPC分类号： G11C1700
CPC分类号： G11C17/16
摘要： A memory system is provided for accessing an array of polycide fuses. The memory system includes an access control circuit configured to individually program and read each of the polycide fuses in the array. Row and column decoding circuitry is provided to selectively connect one of the polycide fuses to the access control circuit in response to an address signal. In one embodiment, the access control circuit includes a partial sense amplifier circuit, which is completed by connecting one of the polycide fuses to the partial sense amplifier circuit. The completed sense amplifier circuit compares the resistance of the connected polycide fuse with a reference resistance to determine the state of the polycide fuse. The completed sense amplifier circuit provides an output signal representative of the state of the connected polycide fuse. The access control circuit also includes a programming transistor connected between an input/output supply voltage (VIO) and the partial sense amplifier circuit. The VIO supply voltage is greater than the VDD supply voltage. When the programming transistor is turned on, the VIO supply voltage is applied to the connected polycide fuse. Under these conditions, the resistance of the connected polycide fuse significantly increases, thereby programming the polycide fuse.
摘要翻译：提供存储系统用于访问多晶硅保险丝阵列。存储器系统包括访问控制电路，其被配置为单独地编程和读取阵列中的每个多晶硅保险丝。行和列解码电路被提供以响应于地址信号选择性地将多存放保险丝之一连接到访问控制电路。在一个实施例中，访问控制电路包括部分读出放大器电路，其通过将多点保险丝之一连接到部分读出放大器电路来完成。完成的读出放大器电路将连接的多晶硅保险丝的电阻与参考电阻进行比较，以确定多晶硅保险丝的状态。完成的读出放大器电路提供表示连接的多晶硅保险丝的状态的输出信号。访问控制电路还包括连接在输入/输出电源电压（VIO）和部分读出放大器电路之间的编程晶体管。 VIO电源电压大于VDD电源电压。当编程晶体管导通时，VIO电源电压被施加到连接的多晶硅保险丝。在这些条件下，连接的多晶硅保险丝的电阻显着增加，从而编程多晶硅保险丝。

6. 发明授权

US6044012A Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process 有权
标题翻译：非易失性存储器阵列采用栅极击穿结构，在标准sub 0.35微米CMOS工艺中
公开(公告)号：US6044012A
公开(公告)日：2000-03-28
申请号：US263375
申请日：1999-03-05
申请人： Kameswara K. Rao , Martin L. Voogel , Shahin Toutounchi , James Karp
发明人： Kameswara K. Rao , Martin L. Voogel , Shahin Toutounchi , James Karp
IPC分类号： G11C17/16 , G11C11/34
CPC分类号： G11C17/16
摘要： A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process. The state of the low voltage storage transistor can be read through the p-channel transistor, or through a dedicated high voltage n-channel transistor. In one embodiment, the programming voltage is generated by a charge pump circuit fabricated in accordance with a standard sub 0.35 micron process. In another embodiment, the decoder circuits that access the non-volatile memory cell use high voltage p-channel transistors to transmit the high programming voltage. Another embodiment of the present invention includes a system-on-a-chip structure that implements the non-volatile memory of the present invention.
摘要翻译：提供了一种非易失性存储单元，其包括具有共同连接到地的源极区和漏极区的低电压CMOS存储晶体管。通过向其栅极施加高编程电压来对低电压存储晶体管进行编程，从而破坏存储晶体管的栅极氧化物。高编程电压通过高压p沟道晶体管施加到低电压存储晶体管。高压p沟道晶体管具有比存储晶体管更厚的栅极氧化物，从而使得p沟道晶体管能够承受更高的电压。高压p沟道晶体管也具有比相同尺寸的高电压n沟道晶体管更高的击穿电压。低电压存储晶体管和高压p沟道晶体管都按照标准的次级0.35微米工艺制造。低电压存储晶体管的状态可以通过p沟道晶体管或通过专用高压n沟道晶体管来读取。在一个实施例中，编程电压由根据标准次级0.35微米工艺制造的电荷泵电路产生。在另一个实施例中，访问非易失性存储单元的解码器电路使用高电压p沟道晶体管来传输高编程电压。本发明的另一实施例包括实现本发明的非易失性存储器的片上系统结构。

7. 发明授权

US06549458B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06549458B1
公开(公告)日：2003-04-15
申请号：US10040044
申请日：2001-10-25
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.
摘要翻译：用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

8. 发明授权

US06522582B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06522582B1
公开(公告)日：2003-02-18
申请号：US09553571
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.
摘要翻译：描述了用于非易失性存储器件的存储单元结构和相关电路。可以使用标准CMOS工艺制造电池结构，例如次0.35微米或次级0.25微米工艺。优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径型源极/漏极区域。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

9. 发明授权

US5949712A Non-volatile memory array using gate breakdown structure 失效
标题翻译：非易失性存储器阵列采用栅极分解结构
公开(公告)号：US5949712A
公开(公告)日：1999-09-07
申请号：US826456
申请日：1997-03-27
申请人： Kameswara K. Rao , Martin L. Voogel
发明人： Kameswara K. Rao , Martin L. Voogel
IPC分类号： G11C5/14 , G11C16/04 , G11C16/10 , G11C17/16 , G11C17/18 , G11C11/34
CPC分类号： G11C16/10 , G11C16/0441 , G11C17/16 , G11C17/18 , G11C5/145
摘要： Non-volatile storage elements are provided in an array on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are one-time programmable devices which are programmed by rupturing their gate oxide.
摘要翻译：在集成电路中的阵列中提供非易失性存储元件，其中非易失性存储元件是低电压CMOS器件，因此在制造意义上与集成电路上的其它类似晶体管兼容，从而不需要特殊类型的晶体管用于非易失性存储。非易失性存储元件是通过破坏其栅极氧化物来编程的一次性可编程器件。

10. 发明授权

US07283409B1 Data monitoring for single event upset in a programmable logic device 有权
标题翻译：可编程逻辑器件中单事件不正常的数据监控
公开(公告)号：US07283409B1
公开(公告)日：2007-10-16
申请号：US11503824
申请日：2006-08-14
申请人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
发明人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/1776
摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.
摘要翻译：描述用于错误检测的数据监视的方法和装置。可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。辅助地址线耦合到与功能发生器相关联的存储器单元组。掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

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