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1. 发明授权

US06549458B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06549458B1
公开(公告)日：2003-04-15
申请号：US10040044
申请日：2001-10-25
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.
摘要翻译：用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

2. 发明授权

US06522582B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06522582B1
公开(公告)日：2003-02-18
申请号：US09553571
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.
摘要翻译：描述了用于非易失性存储器件的存储单元结构和相关电路。可以使用标准CMOS工艺制造电池结构，例如次0.35微米或次级0.25微米工艺。优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径型源极/漏极区域。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

3. 发明授权

US07452765B1 Single event upset in SRAM cells in FPGAs with high resistivity gate structures 有权
标题翻译：在具有高电阻率栅极结构的FPGA中的SRAM单元中的单事件不正常
公开(公告)号：US07452765B1
公开(公告)日：2008-11-18
申请号：US11242409
申请日：2005-09-30
申请人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
发明人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
IPC分类号： H01L21/8238
CPC分类号： H01L27/11803 , H01L21/76831 , H01L21/76834 , H01L27/11
摘要： SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
摘要翻译： SEU硬化串联电阻负载形成在锁存器的交叉耦合反相器的栅极结构内。对于一些实施例，用于每个交叉耦合的反相器的输入的栅极接触具有足够高的电阻以提供SEU-硬化串联电阻。对于其他实施例，耦合到每个交叉耦合的反相器的输入的导电迹线层包括提供SEU硬化串联电阻的高电阻部分。

4. 发明授权

US06982451B1 Single event upset in SRAM cells in FPGAs with high resistivity gate structures 有权
标题翻译：在具有高电阻率栅极结构的FPGA中的SRAM单元中的单事件不正常
公开(公告)号：US06982451B1
公开(公告)日：2006-01-03
申请号：US10402446
申请日：2003-03-27
申请人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
发明人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
IPC分类号： H01L27/108
CPC分类号： H01L27/11803 , H01L21/76831 , H01L21/76834 , H01L27/11
摘要： SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
摘要翻译： SEU硬化串联电阻负载形成在锁存器的交叉耦合反相器的栅极结构内。对于一些实施例，用于每个交叉耦合的反相器的输入的栅极接触具有足够高的电阻以提供SEU-硬化串联电阻。对于其他实施例，耦合到每个交叉耦合的反相器的输入的导电迹线层包括提供SEU硬化串联电阻的高电阻部分。

5. 发明授权

US07544968B1 Non-volatile memory cell with charge storage element and method of programming 有权
标题翻译：具有电荷存储元件的非易失性存储单元和编程方法
公开(公告)号：US07544968B1
公开(公告)日：2009-06-09
申请号：US11210499
申请日：2005-08-24
申请人： Shahin Toutounchi , James Karp , Jongheon Jeong , Michael G. Ahrens , Michael J. Hart
发明人： Shahin Toutounchi , James Karp , Jongheon Jeong , Michael G. Ahrens , Michael J. Hart
IPC分类号： H01L29/04
CPC分类号： H01L29/42368 , H01L27/1021 , H01L27/112 , H01L27/11206
摘要： An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.
摘要翻译： MOS晶体管被编程在非易失性存储单元中。非易失性存储单元中的存储电容器用于通过在栅极电介质击穿期间向MOS晶体管的编程端提供额外的电荷来提高编程效率，从而避免软编程故障。在特定实施例中，存储电容器是具有比可编程MOS晶体管的介电层更厚的栅介质层的第二MOS晶体管。

6. 发明授权

US06438065B1 Redundancy architecture and method for non-volatile storage 有权
标题翻译：用于非易失性存储的冗余架构和方法
公开(公告)号：US06438065B1
公开(公告)日：2002-08-20
申请号：US09552280
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , Michael J. Hart
发明人： Kameswara K. Rao , Martin L. Voogel , Michael J. Hart
IPC分类号： G11C800
CPC分类号： G11C16/08
摘要： A field programmable gate array (FPGA) includes a first non-volatile memory cell and a second non-volatile memory cell. Each of the two non-volatile memory cells is capable of storing at least one bit of information. The second non-volatile memory cell provides redundant storage of the information stored in the first non-volatile memory cell. A read circuit is coupled to the first non-volatile memory cell and the second non-volatile memory cell. The read circuit simultaneously reads the information stored in the first and second non-volatile memory cells, The read circuit reads the information stored in the first non-volatile memory cell even if the second non-volatile memory cell is defective or is not programmed properly. The FPGA may include a third non-volatile memory cell coupled to the read circuit, which provides redundant storage of the information stored in the first non-volatile memory cell. Each non-volatile memory cell includes a storage transistor having a source and a drain, both of which are coupled to ground. Additionally, each storage transistor has a gate oxide. Each non-volatile memory cell is programmed by breaking the gate oxide of the storage transistor.
摘要翻译：现场可编程门阵列（FPGA）包括第一非易失性存储单元和第二非易失性存储单元。两个非易失性存储器单元中的每一个能够存储至少一个位的信息。第二非易失性存储单元提供存储在第一非易失性存储单元中的信息的冗余存储。读取电路耦合到第一非易失性存储单元和第二非易失性存储单元。读取电路同时读取存储在第一和第二非易失性存储单元中的信息。即使第二非易失性存储器单元有缺陷或未正确编程，读取电路读取存储在第一非易失性存储器单元中的信息。 FPGA可以包括耦合到读取电路的第三非易失性存储器单元，其提供存储在第一非易失性存储器单元中的信息的冗余存储。每个非易失性存储单元包括具有源极和漏极的存储晶体管，二者都耦合到地。另外，每个存储晶体管具有栅极氧化物。通过断开存储晶体管的栅极氧化物来对每个非易失性存储单元进行编程。

7. 发明授权

US06243294B1 Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process 有权
标题翻译：用于非易失性存储的内存架构，使用标准次级0.35微米工艺中的栅极击穿结构
公开(公告)号：US06243294B1
公开(公告)日：2001-06-05
申请号：US09552625
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , Michael J. Hart
发明人： Kameswara K. Rao , Martin L. Voogel , Michael J. Hart
IPC分类号： G11C1604
CPC分类号： G11C16/08
摘要： A field programmable gate array (FPGA) contains an array of memory cells. A word line is coupled to a row of memory cells in the array. A second signal line is coupled to the row of memory cells and extends in parallel with the word line. The second signal line applies a zero voltage to the memory cells when programming a memory cell in the row of memory cells. The second signal line applies a positive voltage to the memory cells when programming a memory cell outside the row of memory cells. Each memory cell is a one-time programmable non-volatile memory cell. Each memory cell includes a storage transistor and an access transistor coupled to one another. The memory cell can be programmed by selecting a word line and a bit line associated with the memory cell being programmed. A zero voltage is applied to a third signal line coupled to the memory cell and extending parallel to the word line. A programming voltage is applied to the selected bit line to program the memory cell.
摘要翻译：现场可编程门阵列（FPGA）包含存储单元阵列。字线耦合到阵列中的一行存储器单元。第二信号线耦合到该行存储器单元并且与字线并行延伸。当对存储器单元行中的存储单元进行编程时，第二信号线向存储器单元施加零电压。当对存储器单元行之外的存储单元进行编程时，第二信号线向存储器单元施加正电压。每个存储单元是一次性可编程非易失性存储单元。每个存储单元包括彼此耦合的存储晶体管和存取晶体管。可以通过选择与被编程的存储器单元相关联的字线和位线来对存储器单元进行编程。零电压被施加到耦合到存储器单元并平行于字线延伸的第三信号线。将编程电压施加到所选位线以对存储器单元进行编程。

8. 发明授权

US07504854B1 Regulating unused/inactive resources in programmable logic devices for static power reduction 有权
标题翻译：调节可编程逻辑器件中的未使用/不活动资源以实现静态功耗的降低
公开(公告)号：US07504854B1
公开(公告)日：2009-03-17
申请号：US10783589
申请日：2004-02-20
申请人： Kevin T. Look , Michael J. Hart , Tim Tuan , Kameswara K. Rao , Robert O. Conn
发明人： Kevin T. Look , Michael J. Hart , Tim Tuan , Kameswara K. Rao , Robert O. Conn
IPC分类号： H03K19/173 , G11C5/14
CPC分类号： H03K19/1778 , G11C5/14 , H03K19/17784
摘要： A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.
摘要翻译：一种操作可编程逻辑器件的方法，包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的一个或多个有效块，以及使用降低的电源电压（例如，½VDD）来操作一个或多个不活动的可编程逻辑器件的块。可以通过高电压n沟道晶体管向可编程逻辑器件的块提供完整的VDD电源电压和降低的电源电压。大于VDD的升压电压被施加到n沟道晶体管的栅极，以向有源块提供完整的VDD电源电压。小于VDD的待机电压被施加到n沟道晶体管的栅极，以向非活动块提供降低的电源电压。可以在可编程逻辑器件的运行时间和/或设计时间期间确定非活动块。

9. 发明授权

US06645802B1 Method of forming a zener diode 有权
标题翻译：形成齐纳二极管的方法
公开(公告)号：US06645802B1
公开(公告)日：2003-11-11
申请号：US09877690
申请日：2001-06-08
申请人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
发明人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
IPC分类号： H01L218234
CPC分类号： H01L27/0251 , Y10S438/983
摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.
摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。齐纳二极管包括阳极和阴极扩散。阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。阳极扩散通过阴极扩散向下延伸到半导体衬底中。阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

10. 发明授权

US06268639B1 Electrostatic-discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US06268639B1
公开(公告)日：2001-07-31
申请号：US09248547
申请日：1999-02-11
申请人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
发明人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
IPC分类号： H01L218222
CPC分类号： H01L27/0251 , Y10S438/983
摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.
摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。齐纳二极管包括阳极和阴极扩散。阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。阳极扩散通过阴极扩散向下延伸到半导体衬底中。阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

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