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1. 发明申请

US20080179691A1 Device Having Pocketless Regions and Method of Making the Device 审中-公开
标题翻译：具有无袖区域的设备及其制造方法
公开(公告)号：US20080179691A1
公开(公告)日：2008-07-31
申请号：US11668946
申请日：2007-01-30
申请人： Kamel Benaissa , Greg Baldwin , Shashank Ekbote
发明人： Kamel Benaissa , Greg Baldwin , Shashank Ekbote
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L21/823412 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/045 , H01L29/1083
摘要： An example of the present application is directed to an integrated circuit having a first plurality of transistors and a second plurality of transistors. Each of the first plurality of transistors comprises a first gate structure oriented in a first direction and each of the second plurality of transistors comprises a second gate structure oriented in a second direction. Each of the first plurality of transistors are formed with at least one more pocket region than each of the second plurality of transistors. Methods for forming the integrated circuit devices of the present application are also disclosed.
摘要翻译：本申请的示例涉及具有第一多个晶体管和第二多个晶体管的集成电路。第一多个晶体管中的每一个包括在第一方向上定向的第一栅极结构，并且第二多个晶体管中的每一个包括沿第二方向取向的第二栅极结构。第一多个晶体管中的每一个形成有比第二多个晶体管中的每个晶体管的至少一个多个袋区域。还公开了用于形成本申请的集成电路器件的方法。

2. 发明申请

US20090263946A1 Device Having Pocketless Regions and Methods of Making the Device 审中-公开
标题翻译：具有无袖区域的设备和制造设备的方法
公开(公告)号：US20090263946A1
公开(公告)日：2009-10-22
申请号：US12493824
申请日：2009-06-29
申请人： Kamel Benaissa , Greg Baldwin , Shashank Ekbote
发明人： Kamel Benaissa , Greg Baldwin , Shashank Ekbote
IPC分类号： H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/045 , H01L29/1083
摘要： An example of the present application is directed to an integrated circuit having a first plurality of transistors and a second plurality of transistors. Each of the first plurality of transistors comprises a first gate structure oriented in a first direction and each of the second plurality of transistors comprises a second gate structure oriented in a second direction. Each of the first plurality of transistors are formed with at least one more pocket region than each of the second plurality of transistors. Methods for forming the integrated circuit devices of the present application are also disclosed.
摘要翻译：本申请的示例涉及具有第一多个晶体管和第二多个晶体管的集成电路。第一多个晶体管中的每一个包括在第一方向上定向的第一栅极结构，并且第二多个晶体管中的每一个包括沿第二方向取向的第二栅极结构。第一多个晶体管中的每一个形成有比第二多个晶体管中的每个晶体管的至少一个多个袋区域。还公开了用于形成本申请的集成电路器件的方法。

3. 发明授权

US08114729B2 Differential poly doping and circuits therefrom 有权
标题翻译：差分多掺杂及其电路
公开(公告)号：US08114729B2
公开(公告)日：2012-02-14
申请号：US11870255
申请日：2007-10-10
申请人： Shashank Ekbote , Kamel Benaissa , Greg C. Baldwin , Borna Obradovic
发明人： Shashank Ekbote , Kamel Benaissa , Greg C. Baldwin , Borna Obradovic
IPC分类号： H01L21/8238
CPC分类号： G11C11/412 , H01L21/26513 , H01L21/28052 , H01L21/32155 , H01L21/823842 , H01L27/0922 , Y10S257/903
摘要： A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant.
摘要翻译：一种制造CMOS集成电路的方法及其集成电路包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，以及在栅极电介质上形成多晶硅。多晶硅层的一部分被掩蔽，并且执行第一掺杂剂类型的预栅极蚀刻注入到多晶硅层的未屏蔽部分中，其中多晶硅层的掩模部分被保护免受第一掺杂剂的影响。多晶硅层被图案化以形成多个多晶硅栅极和多条多晶硅线，其中掩模部分包括将PMOS器件的多晶硅栅极耦合到NMOS器件的多晶硅栅极的至少一条多晶硅线路。然后完成集成电路的制造，其中集成电路包括形成在掩模部分中的至少一个第一区域，该第一区域在预栅极蚀刻植入物的多晶硅栅极中缺少第一掺杂剂，以及形成在未掩模部分中的至少一个第二区域在栅极蚀刻植入物的多晶硅栅极中具有第一掺杂剂。

4. 发明申请

US20090096031A1 DIFFERENTIAL POLY DOPING AND CIRCUITS THEREFROM 有权
标题翻译：差分多重聚合和电路
公开(公告)号：US20090096031A1
公开(公告)日：2009-04-16
申请号：US11870255
申请日：2007-10-10
申请人： Shashank EKBOTE , Kamel Benaissa , Greg C. Baldwin , Borna Obradovic
发明人： Shashank EKBOTE , Kamel Benaissa , Greg C. Baldwin , Borna Obradovic
IPC分类号： H01L27/11 , H01L21/3205
CPC分类号： G11C11/412 , H01L21/26513 , H01L21/28052 , H01L21/32155 , H01L21/823842 , H01L27/0922 , Y10S257/903
摘要： A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant.
摘要翻译：一种制造CMOS集成电路的方法及其集成电路包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，以及在栅极电介质上形成多晶硅。多晶硅层的一部分被掩蔽，并且执行第一掺杂剂类型的预栅极蚀刻注入到多晶硅层的未屏蔽部分中，其中多晶硅层的掩模部分被保护免受第一掺杂剂的影响。多晶硅层被图案化以形成多个多晶硅栅极和多条多晶硅线，其中掩模部分包括将PMOS器件的多晶硅栅极耦合到NMOS器件的多晶硅栅极的至少一条多晶硅线路。然后完成集成电路的制造，其中集成电路包括形成在掩模部分中的至少一个第一区域，该第一区域在预栅极蚀刻植入物的多晶硅栅极中缺少第一掺杂剂，以及形成在未掩模部分中的至少一个第二区域在栅极蚀刻植入物的多晶硅栅极中具有第一掺杂剂。

5. 发明授权

US08940598B2 Low temperature coefficient resistor in CMOS flow 有权
标题翻译： CMOS流量中的低温系数电阻
公开(公告)号：US08940598B2
公开(公告)日：2015-01-27
申请号：US13288700
申请日：2011-11-03
申请人： Greg Charles Baldwin , Kamel Benaissa , Sarah Liu , Song Zhao
发明人： Greg Charles Baldwin , Kamel Benaissa , Sarah Liu , Song Zhao
IPC分类号： H01L21/8238 , H01L27/06
CPC分类号： H01L28/22 , G06F17/5072 , G06F17/5081 , H01L21/265 , H01L21/8238 , H01L27/0629 , H02J7/0044 , H02J7/025
摘要： A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.
摘要翻译：一种将低TCR电阻添加到基准CMOS制造流程的方法。在CMOS制造流程中形成低TCR电阻器的方法。在CMOS制造流程中形成具有低TCR电阻器的n型和p型晶体管的方法。

6. 发明授权

US07053465B2 Semiconductor varactor with reduced parasitic resistance 有权
标题翻译：半导体变容二极管具有降低的寄生电阻
公开(公告)号：US07053465B2
公开(公告)日：2006-05-30
申请号：US09994421
申请日：2001-11-27
申请人： Kamel Benaissa , Chi-Cheong Shen
发明人： Kamel Benaissa , Chi-Cheong Shen
IPC分类号： H01L29/76
CPC分类号： H01L27/0808 , H01L29/94
摘要： A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.
摘要翻译：具有降低的寄生电阻的半导体变容二极管。在阱区（20）中形成接触隔离结构（32）。栅极接触结构（70）形成在接触隔离结构（32）的上方，从而减小寄生电阻。此外，在阱区（20）上的栅极层（50）上形成接触结构是进一步的实施例，以减小寄生电阻。

7. 发明授权

US07994009B2 Low cost transistors using gate orientation and optimized implants 有权
标题翻译：低成本晶体管采用栅极取向和优化的植入
公开(公告)号：US07994009B2
公开(公告)日：2011-08-09
申请号：US12492743
申请日：2009-06-26
申请人： Kamel Benaissa , Greg C. Baldwin , Shaofeng Yu , Shashank S. Ekbote
发明人： Kamel Benaissa , Greg C. Baldwin , Shaofeng Yu , Shashank S. Ekbote
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L29/66537 , H01L29/6659 , H01L29/66659
摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.
摘要翻译：公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜角度，剂量和/或旋转之间的能量。由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。还公开了同时制造这两种晶体管的工艺。公开了同时形成对称和不对称晶体管的工艺的具体实施例。

8. 发明申请

US20100244138A1 SEMICONDUCTOR VARACTOR WITH REDUCED PARASITIC RESISTANCE 审中-公开
标题翻译：具有降低隔离电阻的半导体变送器
公开(公告)号：US20100244138A1
公开(公告)日：2010-09-30
申请号：US12796206
申请日：2010-06-08
申请人： Kamel Benaissa , Chi-Cheong Shen
发明人： Kamel Benaissa , Chi-Cheong Shen
IPC分类号： H01L29/78
CPC分类号： H01L27/0808 , H01L29/94
摘要： A semiconductor varactor with reduced parasitic resistance is disclosed. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) in a further embodiment to reduce the parasitic resistance.
摘要翻译：公开了具有降低的寄生电阻的半导体变容二极管。在阱区（20）中形成接触隔离结构（32）。栅极接触结构（70）形成在接触隔离结构（32）的上方，从而减小寄生电阻。此外，在另一实施例中，在阱区（20）上的栅极层（50）上形成接触结构以减小寄生电阻。

9. 发明授权

US08294243B2 Lateral bipolar transistor with compensated well regions 有权
标题翻译：具有补偿井区的侧向双极晶体管
公开(公告)号：US08294243B2
公开(公告)日：2012-10-23
申请号：US12941415
申请日：2010-11-08
申请人： Kamel Benaissa
发明人： Kamel Benaissa
IPC分类号： H01L27/02
CPC分类号： H01L29/7393 , H01L29/66325
摘要： Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.
摘要翻译：源极和漏极或发射极和集电极区域之间的导通是晶体管工作中的一个重要特性，特别是对于横向双极晶体管。因此，可以促进对该特性的控制的技术可以通过促进具有展现期望的操作性能的可能性增加的晶体管的生产来减轻产量损失。如本文所公开的，在半导体衬底中建立阱区，以便于除了别的以外，有助于控制横向双极晶体管的源极和漏极区之间的传导，从而减轻产量损失和其它相关的制造缺陷。重要的是，在建立井区域时不需要额外的掩模，从而进一步降低（增加）与促进期望的设备性能相关的成本。

10. 发明申请

US20110049678A1 LATERAL BIPOLAR TRANSISTOR WITH COMPENSATED WELL REGIONS 有权
标题翻译：具有补偿井区的侧向双极晶体管
公开(公告)号：US20110049678A1
公开(公告)日：2011-03-03
申请号：US12941415
申请日：2010-11-08
申请人： Kamel Benaissa
发明人： Kamel Benaissa
IPC分类号： H01L29/73
CPC分类号： H01L29/7393 , H01L29/66325
摘要： Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.
摘要翻译：源极和漏极或发射极和集电极区域之间的导通是晶体管工作中的一个重要特性，特别是对于横向双极晶体管。因此，可以促进对该特性的控制的技术可以通过促进具有展现期望的操作性能的可能性增加的晶体管的生产来减轻产量损失。如本文所公开的，在半导体衬底中建立阱区，以便于除了别的以外，有助于控制横向双极晶体管的源极和漏极区之间的传导，从而减轻产量损失和其它相关的制造缺陷。重要的是，在建立井区域时不需要额外的掩模，从而进一步降低（增加）与促进期望的设备性能相关的成本。

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