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    • 10. 发明申请
    • Versatile system for limiting electric field degradation of semiconductor structures
    • 用于限制半导体结构电场退化的通用系统
    • US20050258494A1
    • 2005-11-24
    • US10850751
    • 2004-05-21
    • PR ChidambaramGreg Baldwin
    • PR ChidambaramGreg Baldwin
    • H01L21/302H01L23/62H01L29/06H01L29/08H01L29/78
    • H01L29/0847H01L29/0653H01L29/7833H01L29/7835H01L29/7836
    • The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.
    • 本发明提供了一种用于限制由在第二半导体结构(310)上由高电压从半导体衬底(302)内部产生的电场(314)引起的第一半导体结构(304)劣化的系统。 半导体器件(300)适于将如在结构304处实现的场的有效幅度减小到一些分数分量(320),或者使得该场接近第一结构的角度(322) 第一衬底区域(306) - 突出。 本发明的某些实施例提供:第一半导体结构的侧向凹陷以邻接设置在第二半导体结构和第一基底区域之间的隔离结构(312); 所述第一半导体结构从所述隔离结构侧向退缩,以在其间形成护城河; 和在第一衬底区域内的反掺杂区域(316)。