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1. 发明申请

US20030026160A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20030026160A1
公开(公告)日：2003-02-06
申请号：US10265728
申请日：2002-10-08
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C005/14
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device comprises an integrated circuit provided in a semiconductor chip and setting information memory. The setting information memory stores operation/function setting information of the integrated circuit and receives a signal generated based on power-on in reading out the operation/function setting information.

2. 发明申请

US20020097596A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20020097596A1
公开(公告)日：2002-07-25
申请号：US10086869
申请日：2002-03-04
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeru Atsumi , Hironori Banba
IPC分类号： G11C005/06 , G11C011/34
CPC分类号： G11C16/16 , G11C16/08
摘要： A nonvolatile semiconductor memory device comprises a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of 0V or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode. A source-to-drain current path of the first P-channel MOS transistor is connected in parallel to the source-to-drain current path of the first N-channel MOS transistor, and a source-to-drain current path of the second P-channel MOS transistor is connected in parallel to the source-to-drain current path of the second N-channel MOS transistor.
摘要翻译：非易失性半导体存储器件包括具有第一和第二N沟道MOS晶体管的行解码器电路和对应于每条字线的第一和第二P沟道MOS晶体管。第一N沟道MOS晶体管的源极 - 漏极电流路径的一端连接到字线，并且其另一端连接到预解码器电路的对应的一个输出端。第二N沟道MOS晶体管的源极 - 漏极电流路径的一端连接到字线，并且其另一端在数据擦除模式下被提供0V以上的电压，并被提供有低数据擦除模式以外的模式下的低逻辑电平信号。第一P沟道MOS晶体管的源极 - 漏极电流路径并联连接到第一N沟道MOS晶体管的源极 - 漏极电流路径，并且第二P沟道MOS晶体管的源极 - 漏极电流路径 P沟道MOS晶体管与第二N沟道MOS晶体管的源极 - 漏极电流路径并联连接。

3. 发明申请

US20040136239A1 Semiconductor integrated circuit device with erasable and programmable fuse memory 失效
标题翻译：具有可擦除和可编程保险丝存储器的半导体集成电路器件
公开(公告)号：US20040136239A1
公开(公告)日：2004-07-15
申请号：US10743385
申请日：2003-12-23
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C016/04
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.
摘要翻译：半导体集成电路器件包括非易失性存储单元，接收地电位的单元的源极和接收第一控制信号的单元的栅极; 晶体管，晶体管的源极，接收所述单元的漏极电位，以及所述晶体管的栅极接收第二控制信号; 和控制器。控制器接收在检测到电源接通时产生的第三控制信号，并输出第一和第二控制信号。第一控制信号的电位从接地电位变化到在第一时间段期间保持的接地电位不同的电位，并且第二控制信号的电位从地电势变为不同于地电位，在第二段时间内保持。

4. 发明申请

US20020027452A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20020027452A1
公开(公告)日：2002-03-07
申请号：US09977294
申请日：2001-10-16
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： H03K005/153
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device comprises an integrated circuit provided in a semiconductor chip and setting information memory. The setting information memory stores operation/function setting information of the integrated circuit and receives a signal generated based on power-on in reading out the operation/function setting information.
摘要翻译：半导体集成电路器件包括设置在半导体芯片中的集成电路和设置信息存储器。设置信息存储器存储集成电路的操作/功能设置信息，并且在读取操作/功能设置信息时接收基于通电的信号。

5. 发明申请

US20020021611A1 Power supply circuit and semiconductor memory device having the same 失效
标题翻译：电源电路和半导体存储器件具有相同的功能
公开(公告)号：US20020021611A1
公开(公告)日：2002-02-21
申请号：US09983258
申请日：2001-10-23
申请人： Kabushiki Kaisha Toshiba
发明人： Hironori Banba , Shigeru Atsumi
IPC分类号： G11C005/14
CPC分类号： G11C16/30 , G11C5/145 , H02M3/073
摘要： A number of booster circuits to be operated out of a plurality of booster circuits are selected in accordance with a level of the boosted voltage to be provided at a common voltage output terminal of the plurality of booster circuits. With such an arrangement, fluctuations in the output voltage that can appear when a light load is applied to the voltage output terminal of the booster circuits can be effectively reduced to make the semiconductor memory device driven by the power supply circuit operate reliably. Further, one of the output terminals of intermediate voltage booster circuits is connected to the output terminal of a high voltage booster circuit. Then, a desired voltage can be obtained from the booster circuits that are implemented without using costly transistors to reduce the chip cost.
摘要翻译：根据要提供在多个升压电路的公共电压输出端的升压电压的电平来选择要从多个升压电路中操作的多个升压电路。通过这样的布置，可以有效地减少当将轻负载施加到升压电路的电压输出端子时可以出现的输出电压的波动，使由电源电路驱动的半导体存储器件可靠地工作。此外，中压升压电路的输出端之一连接到高压升压电路的输出端。然后，可以从不使用昂贵的晶体管而实现的升压电路获得期望的电压以降低芯片成本。

6. 发明申请

US20020014909A1 Pump circuit boosting a supply voltage 失效
公开(公告)号：US20020014909A1
公开(公告)日：2002-02-07
申请号：US09972905
申请日：2001-10-10
申请人： Kabushiki Kaisha Toshiba
发明人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
IPC分类号： G05F001/10
CPC分类号： H02M3/073
摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.

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