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1. 发明申请

US20030035325A1 Internal voltage generating circuit for periphery, semiconductor memory device having the circuit and method thereof 失效
标题翻译：具有周边的内部电压产生电路，具有该电路的半导体存储器件及其方法
公开(公告)号：US20030035325A1
公开(公告)日：2003-02-20
申请号：US10217799
申请日：2002-08-12
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Hoon Kim , Jae-Youn Youn
IPC分类号： G11C005/14
CPC分类号： G11C5/14 , G11C11/413
摘要： An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address. The internal voltage can be supplied only to peripheral circuits of the banks selected by the bank address, thereby preventing unnecessary power consumption, effectively controlling the internal voltage, and always properly supplying the internal voltage.
摘要翻译：提供了用于存储体外围电路的内部电压发生器，具有内部电压发生器的半导体存储器件，以及用于产生内部电压的方法。根据本发明的可切换内部电压产生电路包括控制部分和内部电压产生电路。控制部分响应于存储体激活命令和用于使能存储体的存储体激活信号产生控制信号。内部电压产生电路接收参考电压，并响应于控制信号输出等于参考电压的内部电压。当组激活命令和存储体激活信号同时使能时，控制信号被使能。银行激活信号是响应于银行地址产生的。只能将内部电压供给由存储体地址选择的存储体的周边电路，从而防止不必要的功耗，有效地控制内部电压，并且始终适当地提供内部电压。

2. 发明申请

US20020067652A1 Apparatus for using volatile memory for long-term storage 有权
标题翻译：用于使用易失性存储器进行长期存储的设备
公开(公告)号：US20020067652A1
公开(公告)日：2002-06-06
申请号：US09728457
申请日：2000-12-01
申请人： Genatek, Inc.
发明人： Jason R. Caulkins
IPC分类号： G11C005/14
CPC分类号： G06F1/30
摘要： A structure including volatile memory devices that are used by the host computer system as the storage media. The volatile memory devices include volatile memory device back up systems to provide power to both the volatile memory and non-volatile memory in the event of power failure. The volatile memory devices also connect directly to an expansion bus of the host computer system, such as a PCI bus. Therefore, the volatile memory devices of the invention include a high-speed path to the host computer system and the volatile memory devices of the invention are faster than prior art devices, use less power and are lower cost.
摘要翻译：包括由主计算机系统用作存储介质的易失性存储器件的结构。易失性存储器件包括易失性存储器件备份系统，以在电源故障的情况下向易失性存储器和非易失性存储器提供电力。易失性存储器件还直接连接到主计算机系统的扩展总线，例如PCI总线。因此，本发明的易失性存储器件包括到主计算机系统的高速路径，并且本发明的易失性存储器件比现有技术的器件更快，使用更少的功率并且成本更低。

3. 发明申请

US20020018390A1 Non-volatile memory with a charge pump with regulated voltage 有权
公开(公告)号：US20020018390A1
公开(公告)日：2002-02-14
申请号：US09909467
申请日：2001-07-19
申请人： STMicroelectronics S.r.I.
发明人： Emanuele Confalonieri , Lorenzo Bedarida , Mauro Sali , Simone Bartoli
IPC分类号： G11C005/14
CPC分类号： G11C16/30
摘要： A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.

4. 发明申请

US20020015349A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20020015349A1
公开(公告)日：2002-02-07
申请号：US09975957
申请日：2001-10-15
申请人： NEC Corporation
发明人： Yoshinori Matsui
IPC分类号： G11C005/14
CPC分类号： G11C7/1048 , G06F12/0893
摘要： The semiconductor integrated circuit device of the present invention is provided with a main memory unit and an auxiliary memory unit which functions as a cache memory, and has a structure which permits bidirectional data transfer via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit; a data transfer bus line precharge power source circuit is provided which supplies to data transfer bus line, when data is not being transferred, a voltage having a level which is lower than the power source voltage supplied to main memory unit. By means of the present invention, it is possible to efficiently conduct data transfer between a main memory unit and an auxiliary memory unit having different operational voltages, and moreover, it is possible to effectively suppress interior noise which is generated.

5. 发明申请

US20040114448A1 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency 失效
标题翻译：具有低功率，高写入延迟模式和高功率，低写入延迟模式和/或独立可选写入延迟的存储器件和方法
公开(公告)号：US20040114448A1
公开(公告)日：2004-06-17
申请号：US10317429
申请日：2002-12-11
发明人： Christopher S. Johnson , Brian Johnson
IPC分类号： G11C005/14
CPC分类号： G11C7/1087 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4093 , G11C2207/2227
摘要： A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.
摘要翻译：逻辑电路在动态随机存取存储器件中以低功率模式，高写延迟模式或高功率模式，低写延迟模式操作写接收器。逻辑电路接收指示高功率，低写入等待时间模式是否已经被使能的第一信号，指示存储器装置中的行存储器单元是否有效的第二信号，指示存储器件正在以断电模式操作，并且指示存储器装置中的读取发送器是否有效的第四信号。只要存储器件中的一行存储器单元处于活动状态，存储器件没有在掉电模式下运行，则只要高功率，低写入延迟模式被使能，逻辑电路就保持写入接收器的电源，读存储器中的发送器不起作用。

6. 发明申请

US20040027866A1 Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation 有权
公开(公告)号：US20040027866A1
公开(公告)日：2004-02-12
申请号：US10633247
申请日：2003-08-01
发明人： Theodore T. Pekny
IPC分类号： G11C005/14
CPC分类号： G11C16/30 , G11C8/08
摘要： A method of operating a memory includes generating a first reference voltage and detecting an active mode of operation of the memory. Upon detection of the active mode, commencing the charging of a node to develop a second reference voltage having a desired value on the node. The word line drive voltage is generated using the first reference voltage while the node is charging the second reference voltage to the desired value. The word line drive voltage is generated using the second reference voltage once the second reference voltage on the node has been charged to the desired value. A standby mode of operation of the memory is detected, and upon detection of the standby mode, the charging of the node is terminated and the word line drive voltage is generated using the first reference voltage.

7. 发明申请

US20030095463A1 Non-volatile semiconductor memory device with enhanced erase/write cycle endurance 失效
标题翻译：具有增强的擦除/写入周期耐久性的非易失性半导体存储器件
公开(公告)号：US20030095463A1
公开(公告)日：2003-05-22
申请号：US10271139
申请日：2002-10-15
发明人： Yasuhiro Shimada , Yoshihisa Kato , Takayoshi Yamada
IPC分类号： G11C005/14
CPC分类号： G11C14/00 , G11C16/30
摘要： The power-supply unit, while directing externally supplied power to the control unit and the like, accumulates an amount of power that is required by the control unit to save data from the volatile memory to the non-volatile memory. When an external power supply has started, the control unit restores data of the non-volatile memory in the volatile memory; and when the external power supply has stopped, the control unit saves data from the volatile memory to the non-volatile memory.
摘要翻译：电源单元在向控制单元等引导外部供电的同时，累积控制单元所需的功率量，以将数据从易失性存储器保存到非易失性存储器。当外部电源开始时，控制单元恢复易失性存储器中的非易失性存储器的数据; 并且当外部电源停止时，控制单元将数据从易失性存储器保存到非易失性存储器。

8. 发明申请

US20030031059A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20030031059A1
公开(公告)日：2003-02-13
申请号：US10272998
申请日：2002-10-18
申请人： FUJITSU LIMITED
发明人： Toru Endo , Shoichiro Kawashima
IPC分类号： G11C005/14
CPC分类号： G11C5/147 , G11C7/14 , G11C11/22
摘要： A semiconductor device includes memory cells of one-transistor one-capacitor connected to nnull1 bit lines that are simultaneously driven, sense amplifiers connected to the nnull1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the nnull1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.

9. 发明申请

US20030026160A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20030026160A1
公开(公告)日：2003-02-06
申请号：US10265728
申请日：2002-10-08
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C005/14
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device comprises an integrated circuit provided in a semiconductor chip and setting information memory. The setting information memory stores operation/function setting information of the integrated circuit and receives a signal generated based on power-on in reading out the operation/function setting information.

10. 发明申请

US20020024867A1 Voltage regulator and data path for a memory device 有权
标题翻译：用于存储器件的稳压器和数据通路
公开(公告)号：US20020024867A1
公开(公告)日：2002-02-28
申请号：US09792553
申请日：2001-02-23
发明人： Brian W. Huber
IPC分类号： G11C005/14
CPC分类号： G11C5/147 , G11C5/145
摘要： One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration. A plurality of delay circuits receives the control pulse and produces a plurality of delayed control pulses. A second logic gate receives the control pulse and the plurality of delayed control pulses and produces a control pulse of extended duration. The control pulse of extended duration may be used, for example, for temporarily sourcing additional current to an output terminal of the voltage regulator. According to another aspect of the present invention, a method is disclosed of forcing a voltage regulator into a low power mode. Another aspect of the present invention is directed to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The signal is then used to enable certain of the output stages in each of the output paths.
摘要翻译：本发明的一个方面涉及一种提高控制在固态存储器件的输出焊盘上出现的电压的晶体管的栅极电压的方法和装置，其中栅极电压由电压调节器通过输出总线提供给多个输出块。周期性地确定对栅极电压的需求，并且当需求高时，总线的每一条线可能暂时连接到电压源。此外，额外的电流临时供应到电压调节器的输出端子。本发明的另一方面涉及一种制造用于电压调节器的延长持续时间的控制脉冲的方法和装置。第一逻辑门接收多个信号，每个信号代表多个输出块之一的电压需求，并产生第一持续时间的控制脉冲。多个延迟电路接收控制脉冲并产生多个延迟的控制脉冲。第二逻辑门接收控制脉冲和多个延迟的控制脉冲，并产生延长的持续时间的控制脉冲。可以使用延长持续时间的控制脉冲，例如用于临时将附加电流提供给电压调节器的输出端子。根据本发明的另一方面，公开了一种将电压调节器强制为低功率模式的方法。本发明的另一方面涉及提供可变输出驱动能力的预驱动器等。预驱动器由两条路径组成，分成输出级。响应于确定随后的输出放大器中的n沟道和p沟道晶体管的相对强度而产生信号。然后，该信号用于启用每个输出路径中的某些输出级。

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