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1. 发明申请

US20200083215A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20200083215A1
公开(公告)日：2020-03-12
申请号：US16255949
申请日：2019-01-24
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
发明人： Hisao Ichijo , Syotaro Ono , Hiroaki Yamashita
IPC分类号： H01L27/02 , H01L23/528 , H01L23/00 , H01L23/49
摘要： A semiconductor device includes a semiconductor body, first to third electrodes provided on the semiconductor body, and a control electrode. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes first to sixth layers. The second layer of a second conductivity type is selectively provided between the first layer of a first conductivity type and the first electrode. The third layer of the first conductivity type is selectively provided between the second layer and the first electrode. The fourth layer of the second conductivity type is provided between the first layer and the second and third electrodes. The fifth layer of the first conductivity type is selectively provided in the fourth layer and electrically connected to the first electrode. The sixth layer of the first conductivity type is provided in the fourth layer, and electrically connected to the third electrode.

2. 发明授权

US10411117B2 Semiconductor device 有权
公开(公告)号：US10411117B2
公开(公告)日：2019-09-10
申请号：US15901994
申请日：2018-02-22
申请人： Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
发明人： Hiroaki Yamashita , Syotaro Ono , Hisao Ichijo
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/10
摘要： A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane, a first semiconductor region of a first conductivity type, a second semiconductor region and a third semiconductor region of a second conductivity type, the first semiconductor region interposed between the third semiconductor region and the second semiconductor region, a first well region of a first conductivity type, a second well region of a first conductivity type separated from the first well region, a first contact region of a first conductivity type, a second contact region of a first conductivity type, a gate electrode provided on the first semiconductor region between the first well region and the second well region, a source electrode having a first region in contact with the first contact region and a second region in contact with the second contact region, and a drain electrode.

3. 发明授权

US09704953B2 Semiconductor device 有权
公开(公告)号：US09704953B2
公开(公告)日：2017-07-11
申请号：US14830980
申请日：2015-08-20
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroaki Yamashita , Syotaro Ono , Hideyuki Ura , Masahiro Shimura
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/66
CPC分类号： H01L29/0696 , H01L29/0634 , H01L29/0688 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L29/7802
摘要： According to one embodiment, a semiconductor device includes a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a gate electrode. An impurity concentration of the second conductivity type of the third semiconductor region is higher than an impurity concentration of the second conductivity type of the second semiconductor regions. The fourth semiconductor region is provided on the first semiconductor regions. The gate electrode provided on the fourth semiconductor region with a gate insulation layer interposed. The gate electrode extends in a third direction. The third direction intersects the first direction. The third direction is parallel to a plane including the first direction and the second direction.

4. 发明申请

US20160254379A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160254379A1
公开(公告)日：2016-09-01
申请号：US14830980
申请日：2015-08-20
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroaki Yamashita , Syotaro Ono , Hideyuki Ura , Masahiro Shimura
IPC分类号： H01L29/78 , H01L29/36 , H01L29/06
CPC分类号： H01L29/0696 , H01L29/0634 , H01L29/0688 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L29/7802
摘要： According to one embodiment, a semiconductor device includes a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a gate electrode. An impurity concentration of the second conductivity type of the third semiconductor region is higher than an impurity concentration of the second conductivity type of the second semiconductor regions. The fourth semiconductor region is provided on the first semiconductor regions. The gate electrode provided on the fourth semiconductor region with a gate insulation layer interposed. The gate electrode extends in a third direction. The third direction intersects the first direction. The third direction is parallel to a plane including the first direction and the second direction.
摘要翻译：根据一个实施例，半导体器件包括多个第一导电类型的第一半导体区域，第二导电类型的多个第二半导体区域，第二导电类型的第三半导体区域，第二导电类型的第四半导体区域导电类型，第一导电类型的第五半导体区域和栅电极。第三半导体区域的第二导电类型的杂质浓度高于第二半导体区域的第二导电类型的杂质浓度。第四半导体区域设置在第一半导体区域上。设置在第四半导体区域上的栅电极具有栅绝缘层。栅电极沿第三方向延伸。第三个方向与第一个方向相交。第三方向平行于包括第一方向和第二方向的平面。

5. 发明授权

US09059284B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09059284B2
公开(公告)日：2015-06-16
申请号：US14107909
申请日：2013-12-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Wataru Saito , Syotaro Ono , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7839 , H01L29/0619 , H01L29/0623 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type. A second semiconductor layer of a second conductivity type is on the first semiconductor layer. A third semiconductor layer is on the second semiconductor layer. A fourth semiconductor layer is selectively in the first semiconductor layer. A first trench and second trench penetrate from a surface of the third layer through the second layer to reach the first layer. An embedded electrode is in the first trench. A control electrode is above the embedded electrode via an insulating film. A lower end of the second trench is connected to the fourth semiconductor layer. A first main electrode is electrically connected to the first layer. A second main electrode is provided in the second trench. A Schottky junction is formed by the first layer and the second main electrode at a sidewall of the second trench.
摘要翻译：半导体器件包括第一导电类型的第一半导体层。第二导电类型的第二半导体层位于第一半导体层上。第三半导体层位于第二半导体层上。第四半导体层选择性地在第一半导体层中。第一沟槽和第二沟槽从第三层的表面穿过第二层穿透到第一层。嵌入式电极在第一沟槽中。控制电极经由绝缘膜在嵌入电极上方。第二沟槽的下端连接到第四半导体层。第一主电极与第一层电连接。第二主电极设置在第二沟槽中。在第二沟槽的侧壁处由第一层和第二主电极形成肖特基结。

6. 发明授权

US09013005B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09013005B2
公开(公告)日：2015-04-21
申请号：US14032007
申请日：2013-09-19
申请人： Kabushiki Kaisha Toshiba
发明人： Syotaro Ono , Wataru Saito , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita , Toshiyuki Naka
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/10
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/42376 , H01L29/4238
摘要： According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.
摘要翻译：根据实施例，半导体器件包括设置在第一半导体层上并包括第一柱和第二柱的第二半导体层。第一控制电极设置在第二半导体层的沟槽中，第二控制电极设置在第二半导体层上并连接到第一控制电极。除了第二控制电极下方的部分之外，在第二半导体层的表面上设置第一半导体区域。第二半导体区域设置在第一半导体区域的表面上，第二半导体区域与第二控制电极下方的部分分开，第三半导体区域设置在第一半导体区域上。第一主电极与第一半导体层电连接，第二主电极与第二和第三半导体区域电连接。

7. 发明申请

US20210305049A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20210305049A1
公开(公告)日：2021-09-30
申请号：US17016600
申请日：2020-09-10
申请人： Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
发明人： Shingo Sato , Yuhki Fujino , Hiroaki Yamashita
IPC分类号： H01L21/22 , H01L29/78 , H01L29/06 , H01L29/10 , H01L29/32 , H01L29/66
摘要： According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region.

8. 发明申请

US20200091335A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20200091335A1
公开(公告)日：2020-03-19
申请号：US16291415
申请日：2019-03-04
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
发明人： Syotaro ONO , Hideto Sugawara , Hiroshi Ohta , Hisao Ichijo , Hiroaki Yamashita
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/66
摘要： According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.

9. 发明申请

US20190109215A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190109215A1
公开(公告)日：2019-04-11
申请号：US15901994
申请日：2018-02-22
申请人： Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
发明人： Hiroaki Yamashita , Syotaro Ono , Hisao Ichijo
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/42376 , H01L29/4238 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane, a first semiconductor region of a first conductivity type, a second semiconductor region and a third semiconductor region of a second conductivity type, the first semiconductor region interposed between the third semiconductor region and the second semiconductor region, a first well region of a first conductivity type, a second well region of a first conductivity type separated from the first well region, a first contact region of a first conductivity type, a second contact region of a first conductivity type, a gate electrode provided on the first semiconductor region between the first well region and the second well region, a source electrode having a first region in contact with the first contact region and a second region in contact with the second contact region, and a drain electrode.

10. 发明授权

US10211331B2 Semiconductor device 有权
公开(公告)号：US10211331B2
公开(公告)日：2019-02-19
申请号：US15252095
申请日：2016-08-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hisao Ichijo , Syotaro Ono , Masahiro Shimura , Hideyuki Ura , Hiroaki Yamashita
IPC分类号： H01L29/739 , H01L29/78 , H01L29/06 , H01L27/06 , H01L49/02
摘要： A semiconductor device includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a second conductivity type third semiconductor region, a first conductivity type fourth semiconductor region, a gate insulating portion, a gate electrode, and first and second electrodes. The first semiconductor region includes first and second portions. The second semiconductor region includes third and fourth portions. The gate electrode is on the gate insulating portion and over the first semiconductor region and a portion of the third semiconductor region. The first electrode is on, and electrically connected to, the fourth semiconductor region. The second electrode is over the first portion, the third portion, and the gate electrode, and spaced from the first electrode.

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