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1. 发明授权

US06906568B2 Hysteresis comparing device with constant hysteresis width and the method thereof 有权
标题翻译：具有恒定滞后宽度的滞后比较装置及其方法
公开(公告)号：US06906568B2
公开(公告)日：2005-06-14
申请号：US10610642
申请日：2003-07-02
申请人： Jyh-fong Lin , Cheng-Kuo Yang
发明人： Jyh-fong Lin , Cheng-Kuo Yang
IPC分类号： H03K3/037 , H03K17/693
CPC分类号： H03K3/0377 , H03K17/693
摘要： A hysteresis comparing device with constant hysteresis width and the method thereof, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch. Also and, under the affection of the environment, a constant hysteresis width can still provided, so that the hysteresis, comparing device can judge the received signals with higher precision.
摘要翻译：具有恒定滞后宽度的滞后比较装置及其方法，其可以分别接收第一信号和第二信号并且可以输出数字信号。滞后比较装置包括阈值电压发生器，多路复用器和下一级比较器。阈值电压发生器用于接收第一信号并输出上阈值电压和较低阈值电压。多路复用器用于接收上阈值电压和下阈值电压，并根据数字信号输出复用信号。多路复用信号是上阈值电压或较低阈值电压。下一级比较器具有用于接收复用信号的一个端子，以及用于接收第二信号的另一终端。下一级比较器输出数字信号。具有恒定滞后宽度的滞后比较装置可以抑制毛刺的影响。此外，在环境的影响下，仍然可以提供恒定的滞后宽度，使得滞后，比较装置可以更高精度地判断接收信号。

2. 发明授权

US06597224B2 Hysteresis comparing device with constant hysteresis width 有权
公开(公告)号：US06597224B2
公开(公告)日：2003-07-22
申请号：US10082214
申请日：2002-02-26
申请人： Jyh-fong Lin , Cheng-Kuo Yang
发明人： Jyh-fong Lin , Cheng-Kuo Yang
IPC分类号： H03K3037
CPC分类号： H03K3/0377 , H03K17/693
摘要： A hysteresis comparing device with constant hysteresis width, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch. Also and, under the affection of the environment, a constant hysteresis width can still provided, so that the hysteresis comparing device can judge the received signals with higher precision.

3. 发明授权

US06463013B1 Clock generating apparatus and method thereof 有权
标题翻译：时钟发生装置及其方法
公开(公告)号：US06463013B1
公开(公告)日：2002-10-08
申请号：US09631293
申请日：2000-08-02
申请人： Kuo-Ping Liu , Jiin Lai , Jyh-fong Lin , Yu-Wei Lin
发明人： Kuo-Ping Liu , Jiin Lai , Jyh-fong Lin , Yu-Wei Lin
IPC分类号： G04F500
CPC分类号： H03L7/199 , G06F1/06 , H03L7/07 , H03L7/23
摘要： A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.
摘要翻译：一种用于产生不同频率的时钟信号的时钟产生装置和方法。时钟发生装置和方法接收和分割主时钟信号以获得参考时钟信号。然后，参考时钟信号和第一反馈时钟信号被锁相以获得第一时钟信号。此外，参考时钟信号和第二反馈时钟信号被锁相以获得第二时钟信号。复位信号和第一时钟信号由分频器接收。然后分频器输出第一反馈时钟信号。另一分频器接收复位信号和第二时钟信号，然后输出第二反馈时钟信号。

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