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1. 发明授权

US6133143A Method of manufacturing interconnect 有权
标题翻译：制造互连的方法
公开(公告)号：US6133143A
公开(公告)日：2000-10-17
申请号：US340928
申请日：1999-06-28
申请人： Jy-Hwang Lin , Ching-Hsing Hsieh , Yueh-Feng Ho , Chia-Chieh Yu
发明人： Jy-Hwang Lin , Ching-Hsing Hsieh , Yueh-Feng Ho , Chia-Chieh Yu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/31133 , H01L21/76802 , H01L21/76814 , H01L21/76877
摘要： The invention provides a method of manufacturing a metal interconnect. A substrate having a metal line formed thereon is provided. An anti-reflection layer is formed on the metal line. A dielectric layer with a relatively low dielectric constant is formed over the substrate. A patterned photoresist layer is formed on the dielectric layer. The patterned photoresist layer has an opening exposing a portion of the dielectric layer. The portion of the dielectric layer exposed by the opening is removed to form a via hole. The patterned photoresist layer is removed by an O.sub.2 --H.sub.2 O--CF.sub.4 plasma. The pressure of the O.sub.2 --H.sub.2 O--CF.sub.4 plasma is about 800-1000 torr. A cleaning process is performed by a post-stripper rinse solution and de-ionized water without using an acetone solution. A barrier layer is formed over the substrate by chemical vapor deposition. A metal nucleation is performed for a long time by chemical vapor deposition to form metal nuclei on the barrier layer. A metal layer is formed to fill the via hole by chemical vapor deposition.
摘要翻译：本发明提供一种制造金属互连的方法。提供其上形成有金属线的基板。在金属线上形成防反射层。在衬底上形成介电常数较低的电介质层。在电介质层上形成图案化的光致抗蚀剂层。图案化的光致抗蚀剂层具有露出电介质层的一部分的开口。通过开口暴露的电介质层的部分被去除以形成通孔。通过O 2 -H 2 O-CF 4等离子体去除图案化的光致抗蚀剂层。 O2-H2O-CF4等离子体的压力约为800-1000乇。在不使用丙酮溶液的情况下，通过脱胶器冲洗溶液和去离子水进行清洁处理。通过化学气相沉积在衬底上形成阻挡层。通过化学气相沉积长时间进行金属成核，以在阻挡层上形成金属核。形成金属层以通过化学气相沉积填充通孔。

2. 发明授权

US6083825A Method of forming unlanded via hole 有权
标题翻译：无凹陷通孔的形成方法
公开(公告)号：US6083825A
公开(公告)日：2000-07-04
申请号：US329113
申请日：1999-06-09
申请人： Jy-Hwang Lin , Yueh-Feng Ho , Pei-Jen Wang
发明人： Jy-Hwang Lin , Yueh-Feng Ho , Pei-Jen Wang
IPC分类号： H01L21/3213 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/32139
摘要： An improved method of fabricating an unlanded via hole on a semiconductor substrate is provided. A conductive line and a patterned anti-reflection coating layer are sequentially formed on the substrate wherein the patterned anti-reflection coating layer has a smaller width than the conductive line and a portion of the conductive layer is exposed by the patterned anti-reflection coating layer. A planarized dielectric layer is formed over the substrate to cover the patterned anti-reflection coating layer and the conductive line. A via hole is formed in the planarized dielectric layer to expose portions of surface and sidewalls of the patterned anti-reflection coating layer as well as the conductive line.
摘要翻译：提供了一种在半导体衬底上制造无衬底通孔的改进方法。在基板上依次形成导电线和图案化的抗反射涂层，其中图案化的抗反射涂层具有比导电线更小的宽度，并且导电层的一部分被图案化的抗反射涂层。平面化介电层形成在衬底上以覆盖图案化的抗反射涂层和导线。在平坦化的电介质层中形成通孔以暴露图案化的抗反射涂层以及导电线的表面和侧壁的部分。

3. 发明授权

US5882537A Metallic precipitate monitoring method 失效
标题翻译：金属沉淀物监测方法
公开(公告)号：US5882537A
公开(公告)日：1999-03-16
申请号：US755905
申请日：1996-11-25
申请人： Yueh-Feng Ho , Chia-Chieh Yu
发明人： Yueh-Feng Ho , Chia-Chieh Yu
IPC分类号： H01L21/3213 , H01L21/00 , H01L21/306
CPC分类号： H01L21/32136
摘要： Disclosed is a method of etching which makes the quantitative analysis possible and easier. In the prior art, chemical plasma etching is mainly by ion bombardment, and the tool used to observe the metal bulk is transmission electron microscopy (TEM), so it is very difficult and complicated to execute quantitative analysis. By using chemical plasma etching, the metal precipitate will be left almost all at the end of etching. Scanning electron microscopy (SEM) is used instead of TEM to perform the quantitative analysis.
摘要翻译：公开了一种使得定量分析成为可能和更容易的蚀刻方法。在现有技术中，化学等离子体蚀刻主要是通过离子轰击，用于观察金属体的工具是透射电子显微镜（TEM），因此执行定量分析是非常困难和复杂的。通过使用化学等离子体蚀刻，在蚀刻结束时金属沉淀将几乎全部残留。使用扫描电子显微镜（SEM）代替TEM进行定量分析。

4. 发明授权

US06258713B1 Method for forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06258713B1
公开(公告)日：2001-07-10
申请号：US09454005
申请日：1999-12-03
申请人： Chia-Chieh Yu , Yueh-Feng Ho
发明人： Chia-Chieh Yu , Yueh-Feng Ho
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a dual damascene structure. A first dielectric layer is formed over a substrate, and then the first dielectric layer is planarized. The first dielectric layer is etched to form a dual damascene opening that includes a via opening and a trench. The via opening exposes a conductive layer in the substrate. A metallic is formed in the via openings and the trenches so that a metallic interconnect and a via are formed at the same time. A cap layer is formed on the metallic layer. An additional etching stop layer may form on the cap layer and the substrate. A second dielectric layer is formed over the substrate. The second dielectric layer is etched to form a via opening that exposes a portion of the cap layer.
摘要翻译：形成双镶嵌结构的方法。第一介电层形成在衬底上，然后第一介电层被平坦化。蚀刻第一电介质层以形成包括通孔开口和沟槽的双镶嵌开口。通孔开口在衬底中暴露导电层。在通路开口和沟槽中形成金属，从而同时形成金属互连和通孔。在金属层上形成盖层。在盖层和衬底上可形成附加的蚀刻停止层。第二介质层形成在衬底上。蚀刻第二电介质层以形成露出帽层的一部分的通孔。

5. 发明申请

US20140264913A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140264913A1
公开(公告)日：2014-09-18
申请号：US13833464
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of second interconnect structures occupying the sub-regions right above the TSV and being configured for electrically coupling the TSV to a higher-level interconnect.
摘要翻译：半导体器件包括衬底，穿透衬底的穿硅通孔（TSV），从顶部穿过TSV的至少一个第一互连结构，并将TSV正上方的区域划分成若干子区域并被配置用于互连路由有源器件和多个第二互连结构占据TSV正上方的子区域并且被配置为将TSV电耦合到较高级互连。

6. 发明授权

US6136694A Method for forming via hole 有权
标题翻译：通孔形成方法
公开(公告)号：US6136694A
公开(公告)日：2000-10-24
申请号：US223330
申请日：1998-12-30
申请人： Yueh-Feng Ho
发明人： Yueh-Feng Ho
IPC分类号： G03F7/42 , H01L21/311 , H01L21/4763
CPC分类号： H01L21/02063 , G03F7/425 , H01L21/31116
摘要： A method for forming a via hole provides a substrate, and a conducting layer is formed on the substrate. An intermetal dielectric layer is deposited conformal to the substrate, and a patterned photoresist is formed on the intermetal dielectric layer. The photoresist is used as a mask, and a portion of intermetal dielectric layer, which is not covered by the photoresist, is removed to expose the conducting layer, so that an opening is formed. A polymer layer is unavoidably formed on the surface of the opening, and then the photoresist and the polymer layer are removed. The residual polymer layer is removed by wet bench to form a via hole.
摘要翻译：形成通孔的方法提供了基板，并且在基板上形成导电层。金属间电介质层与衬底共形沉积，并且在金属间电介质层上形成图案化的光致抗蚀剂。将光致抗蚀剂用作掩模，并且去除未被光致抗蚀剂覆盖的金属间介电层的一部分，以暴露导电层，从而形成开口。在开口的表面上不可避免地形成聚合物层，然后去除光致抗蚀剂和聚合物层。通过湿式台架除去残留的聚合物层以形成通孔。

7. 发明申请

US20140266418A1 Stacked Chip System 有权
标题翻译：堆叠芯片系统
公开(公告)号：US20140266418A1
公开(公告)日：2014-09-18
申请号：US13835055
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/50
CPC分类号： H01L23/50 , H01L23/481 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.
摘要翻译：提供堆叠式芯片系统以包括第一芯片，第二芯片，连接第一芯片和第二芯片的第一组直通硅通孔（TSV），并且包括至少一个第一VSS TSV，至少一个第一VDD TSV，多个第一信号TSV和连接第一芯片和第二芯片的至少一个第一冗余TSV和第二组穿通硅通孔（TSV），并且包括至少一个第二VSS TSV，至少一个第二VDD TSV，多个第二信号TSV和至少一个第二冗余TSV，其中所有所述第一组TSV由被配置为选择所述至少一个第一冗余TSV并绕过所述第一组TSV的其余部分中的至少一个的第一选择电路耦合，以及其中所述至少一个第一冗余TSV和所述至少第二冗余TSV由被配置为允许它们中的一个替换另一个的第二选择电路耦合。

8. 发明申请

US20140264869A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140264869A1
公开(公告)日：2014-09-18
申请号：US13834806
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/532 , H01L23/522
CPC分类号： H01L23/53238 , H01L21/76847 , H01L23/481 , H01L24/05 , H01L24/06 , H01L2224/02331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05023 , H01L2224/05025 , H01L2224/05147 , H01L2224/05149 , H01L2224/05166 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05568 , H01L2224/05582 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/06181 , H01L2224/1134 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953
摘要： A semiconductor device comprises a substrate having a first side with a first surface and a second side with a second surface, a recessed through silicon via (TSV) penetrating the substrate and forming a first step height with respect to the first surface of the first side, a first extruded backside redistribution line (RDL) filling in the first step height and engaging with the recessed through silicon via.
摘要翻译：半导体器件包括具有第一表面和第二表面的第一侧面的衬底，穿过衬底的凹入的硅通孔（TSV），并相对于第一侧面的第一表面形成第一台阶高度，第一挤压后侧再分配线（RDL），其填充在第一级高度并与凹进的硅通孔接合。

9. 发明申请

US20140264918A1 Integrated Circuit Layout 有权
标题翻译：集成电路布局
公开(公告)号：US20140264918A1
公开(公告)日：2014-09-18
申请号：US13834495
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L23/5286 , H01L2224/13 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.
摘要翻译：集成电路布局包括被配置为耦合正工作电压VDD（VDD TSV）的通硅通孔（TSV），被配置为耦合操作信号（信号TSV）的多通硅通孔（TSV）被配置为将VDD TSV和信号TSV以及将VSS TSV连接在一起的一个或多个背面再分配线（RDL）耦合到工作电压VSS（VSS TSV），以形成至少围绕VDD TSV的网状散热结构，并且信号TSV。

10. 发明申请

US20140264915A1 Stacked Integrated Circuit System 审中-公开
标题翻译：堆叠集成电路系统
公开(公告)号：US20140264915A1
公开(公告)日：2014-09-18
申请号：US13833627
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L25/18
CPC分类号： H01L25/18 , G11C5/025 , H01L23/522 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16265 , H01L2224/81191 , H01L2224/81193 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/19104
摘要： A stacked integrated circuit system comprises a first chip with first average pattern density comprising memory cells, a second chip with second average pattern density comprising logic circuitries for the memory cells and a functioning unit and a plurality of through-silicon vias within one of the first chip and second chip to electrically connect the first chip and the second chip, wherein the memory cells of the first chip and the logic circuitries of the second chip are designed to be used collectively in order to perform complete memory functions, and wherein the first average pattern density is higher than the second average pattern density.
摘要翻译：堆叠集成电路系统包括具有包括存储器单元的第一平均图案密度的第一芯片，具有第二平均图案密度的第二芯片，包括用于存储器单元的逻辑电路和功能单元以及在第一和第二芯片之一内的多个穿硅通孔芯片和第二芯片以电连接第一芯片和第二芯片，其中第一芯片的存储器单元和第二芯片的逻辑电路被设计为共同使用以执行完整的存储器功能，并且其中第一平均值图案密度高于第二平均图案密度。

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