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1. 发明申请

US20140264913A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140264913A1
公开(公告)日：2014-09-18
申请号：US13833464
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of second interconnect structures occupying the sub-regions right above the TSV and being configured for electrically coupling the TSV to a higher-level interconnect.
摘要翻译：半导体器件包括衬底，穿透衬底的穿硅通孔（TSV），从顶部穿过TSV的至少一个第一互连结构，并将TSV正上方的区域划分成若干子区域并被配置用于互连路由有源器件和多个第二互连结构占据TSV正上方的子区域并且被配置为将TSV电耦合到较高级互连。

2. 发明授权

US09030025B2 Integrated circuit layout 有权
标题翻译：集成电路布局
公开(公告)号：US09030025B2
公开(公告)日：2015-05-12
申请号：US13834495
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L23/5286 , H01L2224/13 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.
摘要翻译：集成电路布局包括被配置为耦合正工作电压VDD（VDD TSV）的通硅通孔（TSV），被配置为耦合操作信号（信号TSV）的多通硅通孔（TSV）被配置为将VDD TSV和信号TSV以及将VSS TSV连接在一起的一个或多个背面再分配线（RDL）耦合到工作电压VSS（VSS TSV），以形成至少围绕VDD TSV的网状散热结构，并且信号TSV。

3. 发明授权

US08890607B2 Stacked chip system 有权
标题翻译：堆叠芯片系统
公开(公告)号：US08890607B2
公开(公告)日：2014-11-18
申请号：US13835055
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/538 , H01L23/52 , H01L23/50
CPC分类号： H01L23/50 , H01L23/481 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.
摘要翻译：提供堆叠式芯片系统以包括第一芯片，第二芯片，连接第一芯片和第二芯片的第一组直通硅通孔（TSV），并且包括至少一个第一VSS TSV，至少一个第一VDD TSV，多个第一信号TSV和连接第一芯片和第二芯片的至少一个第一冗余TSV和第二组穿通硅通孔（TSV），并且包括至少一个第二VSS TSV，至少一个第二VDD TSV，多个第二信号TSV和至少一个第二冗余TSV，其中所有所述第一组TSV由被配置为选择所述至少一个第一冗余TSV并绕过所述第一组TSV的其余部分中的至少一个的第一选择电路耦合，以及其中所述至少一个第一冗余TSV和所述至少第二冗余TSV由被配置为允许它们中的一个替换另一个的第二选择电路耦合。

4. 发明申请

US20140264630A1 Integrated Structure 审中-公开
标题翻译：综合结构
公开(公告)号：US20140264630A1
公开(公告)日：2014-09-18
申请号：US13832844
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated structure comprises a substrate with a first dielectric layer and a second dielectric cap layer disposed thereon in sequence, a metal gate transistor with a high-k gate dielectric layer on the substrate, a gate electrode embedded within the first dielectric layer and a source/drain within the substrate, a first metal contact penetrating the first dielectric layer and being in direct contact with the source/drain and a through-silicon via penetrating the second dielectric cap layer, the first dielectric layer and the substrate.
摘要翻译：集成结构包括依次包括第一电介质层和第二电介质盖层的衬底，在衬底上具有高k栅极电介质层的金属栅极晶体管，嵌入在第一介电层内的栅电极和源极 /漏极，穿过第一介电层并与源极/漏极直接接触的第一金属触点和穿过第二电介质盖层，第一电介质层和衬底的贯穿硅。

5. 发明申请

US20140264918A1 Integrated Circuit Layout 有权
标题翻译：集成电路布局
公开(公告)号：US20140264918A1
公开(公告)日：2014-09-18
申请号：US13834495
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L23/5286 , H01L2224/13 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.
摘要翻译：集成电路布局包括被配置为耦合正工作电压VDD（VDD TSV）的通硅通孔（TSV），被配置为耦合操作信号（信号TSV）的多通硅通孔（TSV）被配置为将VDD TSV和信号TSV以及将VSS TSV连接在一起的一个或多个背面再分配线（RDL）耦合到工作电压VSS（VSS TSV），以形成至少围绕VDD TSV的网状散热结构，并且信号TSV。

6. 发明申请

US20140264915A1 Stacked Integrated Circuit System 审中-公开
标题翻译：堆叠集成电路系统
公开(公告)号：US20140264915A1
公开(公告)日：2014-09-18
申请号：US13833627
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L25/18
CPC分类号： H01L25/18 , G11C5/025 , H01L23/522 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16265 , H01L2224/81191 , H01L2224/81193 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/19104
摘要： A stacked integrated circuit system comprises a first chip with first average pattern density comprising memory cells, a second chip with second average pattern density comprising logic circuitries for the memory cells and a functioning unit and a plurality of through-silicon vias within one of the first chip and second chip to electrically connect the first chip and the second chip, wherein the memory cells of the first chip and the logic circuitries of the second chip are designed to be used collectively in order to perform complete memory functions, and wherein the first average pattern density is higher than the second average pattern density.
摘要翻译：堆叠集成电路系统包括具有包括存储器单元的第一平均图案密度的第一芯片，具有第二平均图案密度的第二芯片，包括用于存储器单元的逻辑电路和功能单元以及在第一和第二芯片之一内的多个穿硅通孔芯片和第二芯片以电连接第一芯片和第二芯片，其中第一芯片的存储器单元和第二芯片的逻辑电路被设计为共同使用以执行完整的存储器功能，并且其中第一平均值图案密度高于第二平均图案密度。

7. 发明申请

US20140264912A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20140264912A1
公开(公告)日：2014-09-18
申请号：US13833129
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L23/49844 , H01L23/522 , H01L23/5221 , H01L23/528 , H01L23/5384 , H01L23/5386 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.
摘要翻译：半导体器件包括衬底，穿透衬底的穿硅通孔（TSV），在TSV正上方的多个第一互连结构，被配置为将TSV电耦合到较高级互连，跨越第二互连结构 TSV，并且被配置用于在TSV正上方的有源器件和多个虚设金属图案的互连布线，其与TSV，第一互连结构和第二互连结构电隔离。

8. 发明申请

US20140266418A1 Stacked Chip System 有权
标题翻译：堆叠芯片系统
公开(公告)号：US20140266418A1
公开(公告)日：2014-09-18
申请号：US13835055
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/50
CPC分类号： H01L23/50 , H01L23/481 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.
摘要翻译：提供堆叠式芯片系统以包括第一芯片，第二芯片，连接第一芯片和第二芯片的第一组直通硅通孔（TSV），并且包括至少一个第一VSS TSV，至少一个第一VDD TSV，多个第一信号TSV和连接第一芯片和第二芯片的至少一个第一冗余TSV和第二组穿通硅通孔（TSV），并且包括至少一个第二VSS TSV，至少一个第二VDD TSV，多个第二信号TSV和至少一个第二冗余TSV，其中所有所述第一组TSV由被配置为选择所述至少一个第一冗余TSV并绕过所述第一组TSV的其余部分中的至少一个的第一选择电路耦合，以及其中所述至少一个第一冗余TSV和所述至少第二冗余TSV由被配置为允许它们中的一个替换另一个的第二选择电路耦合。

9. 发明申请

US20140264869A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140264869A1
公开(公告)日：2014-09-18
申请号：US13834806
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/532 , H01L23/522
CPC分类号： H01L23/53238 , H01L21/76847 , H01L23/481 , H01L24/05 , H01L24/06 , H01L2224/02331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05023 , H01L2224/05025 , H01L2224/05147 , H01L2224/05149 , H01L2224/05166 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05568 , H01L2224/05582 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/06181 , H01L2224/1134 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953
摘要： A semiconductor device comprises a substrate having a first side with a first surface and a second side with a second surface, a recessed through silicon via (TSV) penetrating the substrate and forming a first step height with respect to the first surface of the first side, a first extruded backside redistribution line (RDL) filling in the first step height and engaging with the recessed through silicon via.
摘要翻译：半导体器件包括具有第一表面和第二表面的第一侧面的衬底，穿过衬底的凹入的硅通孔（TSV），并相对于第一侧面的第一表面形成第一台阶高度，第一挤压后侧再分配线（RDL），其填充在第一级高度并与凹进的硅通孔接合。

10. 发明授权

US08283110B2 Method for fabricating an image sensor device 有权
标题翻译：图像传感器装置的制造方法
公开(公告)号：US08283110B2
公开(公告)日：2012-10-09
申请号：US12816743
申请日：2010-06-16
申请人： Ming-Sheng Yang , Ya-Yun Yu
发明人： Ming-Sheng Yang , Ya-Yun Yu
IPC分类号： G03F7/20
CPC分类号： H01L27/14685 , H01L27/14627 , H01L27/14698
摘要： A method for fabricating an image sensor device is disclosed. The method for fabricating an image sensor device comprises forming a photosensitive layer on a substrate. The photosensitive layer is exposed through a first photomask to form an exposed portion and an unexposed portion. The unexposed portion is partially exposed through a second photomask to form a trimmed part, wherein the second photomask comprise a first segment and a second segment that has a transmittance greater than that of the first segment. The trimmed part is removed to form photosensitive structures. The photosensitive structures are reflowed to form a first microlens and a second microlens having different heights.
摘要翻译：公开了一种用于制造图像传感器装置的方法。图像传感器装置的制造方法包括在基板上形成感光层。感光层通过第一光掩模曝光以形成曝光部分和未曝光部分。未曝光部分通过第二光掩模部分曝光以形成修剪部分，其中第二光掩模包括第一光栅和第二光栅，其具有大于第一光栅的透射率。去除修剪的部分以形成光敏结构。光敏结构被回流以形成具有不同高度的第一微透镜和第二微透镜。

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