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1. 发明申请

US20120208342A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120208342A1
公开(公告)日：2012-08-16
申请号：US13455633
申请日：2012-04-25
申请人： Jusuke OGURA , Hikaru KOKURA , Hideyuki KOJIMA , Toru ANEZAKI , Hiroyuki OGAWA , Junichi ARIYOSHI
发明人： Jusuke OGURA , Hikaru KOKURA , Hideyuki KOJIMA , Toru ANEZAKI , Hiroyuki OGAWA , Junichi ARIYOSHI
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/1052 , H01L27/11521
摘要： A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
摘要翻译：制造半导体器件的方法包括在半导体衬底中形成限定有源区的隔离区，在半导体衬底上形成第一绝缘膜，形成第二绝缘膜，该第二绝缘膜具有与第一绝缘膜相同的蚀刻性能绝缘膜，通过使用基于碳氟化合物的蚀刻气体的干蚀刻从有源区域和隔离区域上的第一区域选择性地去除第二绝缘膜，通过在第一绝缘膜上暴露于第一绝缘膜上形成的残留膜含氧的气氛，通过湿式蚀刻从第一区域选择性地除去第一绝缘膜。

2. 发明申请

US20080067599A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080067599A1
公开(公告)日：2008-03-20
申请号：US11944073
申请日：2007-11-21
申请人： Tomohiko TSUTSUMI , Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
发明人： Tomohiko TSUTSUMI , Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
IPC分类号： H01L23/62 , H01L21/336
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
摘要翻译：半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

3. 发明申请

US20110111567A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110111567A1
公开(公告)日：2011-05-12
申请号：US13010416
申请日：2011-01-20
申请人： Tomohiko TSUTSUMI , Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
发明人： Tomohiko TSUTSUMI , Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
IPC分类号： H01L21/8234
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
摘要翻译：半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

4. 发明申请

US20100320543A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100320543A1
公开(公告)日：2010-12-23
申请号：US12854300
申请日：2010-08-11
申请人： Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
发明人： Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
IPC分类号： H01L27/11
CPC分类号： H01L21/823857 , H01L21/823892 , H01L27/0629
摘要： A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
摘要翻译：半导体器件制造方法包括：在半导体衬底中形成具有1以上的纵横比的隔离区域，形成栅极绝缘膜，形成硅栅电极和硅电阻元件，在栅电极上形成侧壁间隔物，用磷和第二有源区掺杂第一有源区，通过离子注入掺杂p型杂质的电阻元件，在500℃或更低的温度下形成自对准硅化物块，沉积覆盖自对准硅化物块的金属层，并选择性地形成金属硅化物层。该方法可以进一步包括：形成厚和薄的栅极绝缘膜，并且执行不穿透厚栅极绝缘膜的第一导电类型的离子的注入和相反导电类型的离子的倾斜注入也穿透厚栅极绝缘膜在形成侧壁间隔物之前。

5. 发明申请

US20110198707A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110198707A1
公开(公告)日：2011-08-18
申请号：US13075625
申请日：2011-03-30
申请人： Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
发明人： Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823892 , H01L27/0629
摘要： A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500 ° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
摘要翻译：半导体器件制造方法包括：在半导体衬底中形成具有1以上的纵横比的隔离区域，形成栅极绝缘膜，形成硅栅电极和硅电阻元件，在栅电极上形成侧壁间隔物，用磷和第二有源区掺杂第一有源区，通过离子注入掺杂p型杂质的电阻元件，在500℃或更低的温度下形成自对准硅化物块，沉积覆盖自对准硅化物块的金属层，并选择性地形成金属硅化物层。该方法可以进一步包括：形成厚和薄的栅极绝缘膜，并且执行不穿透厚栅极绝缘膜的第一导电类型的离子的注入和相反导电类型的离子的倾斜注入也穿透厚栅极绝缘膜在形成侧壁间隔物之前。

6. 发明申请

US20080237690A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080237690A1
公开(公告)日：2008-10-02
申请号：US12055708
申请日：2008-03-26
申请人： Toru ANEZAKI , Kenichi OKABE
发明人： Toru ANEZAKI , Kenichi OKABE
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11526 , H01L21/823814 , H01L27/105 , H01L27/11546
摘要： To provide a semiconductor device in which a high-performance and high-breakdown-voltage p-channel type MOS transistor having a surface channel structure and a memory cell are formed on the same substrate, and a method of manufacturing the semiconductor device. A method of manufacturing a semiconductor device including a stacked gate type nonvolatile memory cell and a p-channel type first transistor, includes: forming a gate insulating film of the first transistor on a semiconductor substrate; forming a tunnel insulating film of the stacked gate type nonvolatile memory cell on the semiconductor substrate; forming a first conductive layer containing an n-type impurity on the tunnel insulating film and the gate insulating film; and implanting p-type impurity ions to a region of the first conductive layer for forming the first transistor to turn the region of the first conductive layer into a p-type region.
摘要翻译：为了提供一种半导体器件，其中在相同的衬底上形成具有表面沟道结构和存储单元的高性能和高耐压P沟道型MOS晶体管及其制造方法。一种制造包括堆叠栅极型非易失性存储单元和p沟道型第一晶体管的半导体器件的方法，包括：在半导体衬底上形成第一晶体管的栅极绝缘膜; 在所述半导体衬底上形成所述层叠栅型非易失性存储单元的隧道绝缘膜; 在隧道绝缘膜和栅极绝缘膜上形成含有n型杂质的第一导电层; 以及将p型杂质离子注入到所述第一导电层的区域中以形成所述第一晶体管，以将所述第一导电层的区域转变为p型区域。

7. 发明申请

US20090039411A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090039411A1
公开(公告)日：2009-02-12
申请号：US12187851
申请日：2008-08-07
申请人： Toru ANEZAKI
发明人： Toru ANEZAKI
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L21/823462 , H01L21/823418 , H01L21/823481 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： According to an aspect of an embodiment, a semiconductor device has a substrate a first insulator formed in a first area of the substrate, and a second insulator formed in the second area of the substrate, a first transistor formed over a first device region surrounded by the first area, the first transistor having a first gate insulating film having a first thickness, the first gate insulating film being formed over the first device region, a first gate electrode formed over the first gate insulating film and the second transistor having a second gate insulating film formed over the second device region, a second gate insulating film having a second thickness less than the first thickness of the first gate insulating film, a second gate electrode formed over the second gate insulating film.
摘要翻译：根据实施例的一个方面，半导体器件具有衬底，该衬底形成在衬底的第一区域中的第一绝缘体和形成在衬底的第二区域中的第二绝缘体，第一晶体管形成在由所述第一区域，所述第一晶体管具有第一厚度的第一栅极绝缘膜，所述第一栅极绝缘膜形成在所述第一器件区域上，形成在所述第一栅极绝缘膜上的第一栅电极和所述第二栅极具有第二栅极在第二器件区域上形成的绝缘膜，具有小于第一栅极绝缘膜的第一厚度的第二厚度的第二栅极绝缘膜，形成在第二栅极绝缘膜上的第二栅电极。

8. 发明申请

US20080299739A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080299739A1
公开(公告)日：2008-12-04
申请号：US12118245
申请日：2008-05-09
申请人： Kazutaka YOSHIZAWA , Toru ANEZAKI , Katsuaki OOKOSHI , Teruki MORISHITA , Hajime WADA
发明人： Kazutaka YOSHIZAWA , Toru ANEZAKI , Katsuaki OOKOSHI , Teruki MORISHITA , Hajime WADA
IPC分类号： H01L21/76
CPC分类号： H01L21/31612 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/02326 , H01L21/0234 , H01L21/3081 , H01L21/3144 , H01L21/31662 , H01L21/76264 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a first insulating film over a rear surface of a plurality of silicon substrates, annealing the plurality of silicon substrates to degas the oxide species in the first insulating film, and oxidizing the surface of the plurality of silicon substrates in a batch process after annealing the silicon substrates.
摘要翻译：根据实施例的一个方面，制造半导体器件的方法在多个硅衬底的后表面上形成第一绝缘膜，退火多个硅衬底以使第一绝缘膜中的氧化物种类脱气，以及在硅衬底退火之后，以分批工艺氧化多个硅衬底的表面。

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