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1. 发明授权

US08426267B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08426267B2
公开(公告)日：2013-04-23
申请号：US13010416
申请日：2011-01-20
申请人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
摘要翻译：半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

2. 发明申请

US20110108925A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20110108925A1
公开(公告)日：2011-05-12
申请号：US13010255
申请日：2011-01-20
申请人： Tomohiko TSUTSUMI , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko TSUTSUMI , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L27/092
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

3. 发明申请

US20110073950A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20110073950A1
公开(公告)日：2011-03-31
申请号：US12965422
申请日：2010-12-10
申请人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

4. 发明授权

US07755928B2 Semiconductor memory device and semiconductor device group 有权
标题翻译：半导体存储器件和半导体器件组
公开(公告)号：US07755928B2
公开(公告)日：2010-07-13
申请号：US12320861
申请日：2009-02-06
申请人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
发明人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C5/063 , G11C11/412 , H01L27/11 , Y10S257/903
摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.
摘要翻译：半导体器件包括第一CMOS反相器，第二CMOS反相器，第一传输晶体管和第二传输晶体管，其中第一和第二传输晶体管分别形成在由器件隔离区限定在半导体器件上的第一和第二器件区域中，为了彼此并联延伸，第一传输晶体管在第一器件区域上的第一位接触区域处与第一位线接触，第二传输晶体管在第二位线处与第二位线接触，第二位线在第二位接触区域处器件区域，其中第一位接触区域形成在第一器件区域中，使得所述位接触区域的中心朝向第二器件区域偏移，并且其中第二位接触区域形成在第二器件区域中，使得第二位接触区域的中心朝向第一器件区域偏移。

5. 发明授权

US07157330B2 Process for fabricating semiconductor device 有权
标题翻译：半导体器件制造工艺
公开(公告)号：US07157330B2
公开(公告)日：2007-01-02
申请号：US11078519
申请日：2005-03-14
申请人： Osamu Tsuboi , Tomohiko Tsutsumi , Kazutaka Yoshizawa
发明人： Osamu Tsuboi , Tomohiko Tsutsumi , Kazutaka Yoshizawa
IPC分类号： H01L21/8242
CPC分类号： H01L27/10855 , H01L21/31116 , H01L21/76802 , H01L27/10814 , H01L28/91
摘要： A semiconductor device comprising: a first insulation film 60 formed above a base substrate 10; a second insulation film 61 formed on the first insulation film and having different etching characteristics from the first insulation film; and a capacitor 79 including a storage electrode 68 formed on the second insulation film, projected therefrom, the storage electrode being formed, extended downward from side surfaces of the second insulation film. The lower ends of the storage electrodes are formed partially below the etching stopper film, whereby the storage electrodes are fixed by the etching stopper film. Accordingly, the storage electrodes are prevented from peeling off in processing, such as wet etching, etc. The semiconductor device can be fabricated at high yields.
摘要翻译：一种半导体器件，包括：形成在基底基板10上方的第一绝缘膜60; 形成在第一绝缘膜上并且具有与第一绝缘膜不同的蚀刻特性的第二绝缘膜61; 以及电容器79，其包括形成在第二绝缘膜上的存储电极68，从其突出形成有从第二绝缘膜的侧表面向下延伸的存储电极。存储电极的下端部分地形成在蚀刻停止膜的下方，由此通过蚀刻停止膜固定存储电极。因此，防止了诸如湿蚀刻等处理的存储电极的剥离。可以以高产率制造半导体器件。

6. 发明申请

US20050158962A1 Semiconductor device and process for fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050158962A1
公开(公告)日：2005-07-21
申请号：US11078519
申请日：2005-03-14
申请人： Osamu Tsuboi , Tomohiko Tsutsumi , Kazutaka Yoshizawa
发明人： Osamu Tsuboi , Tomohiko Tsutsumi , Kazutaka Yoshizawa
IPC分类号： H01L21/02 , H01L21/311 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10855 , H01L21/31116 , H01L21/76802 , H01L27/10814 , H01L28/91
摘要： A semiconductor device comprising: a first insulation film 60 formed above a base substrate 10; a second insulation film 61 formed on the first insulation film and having different etching characteristics from the first insulation film; and a capacitor 79 including a storage electrode 68 formed on the second insulation film, projected therefrom, the storage electrode being formed, extended downward from side surfaces of the second insulation film. The lower ends of the storage electrodes are formed partially below the etching stopper film, whereby the storage electrodes are fixed by the etching stopper film. Accordingly, the storage electrodes are prevented from peeling off in processing, such as wet etching, etc. The semiconductor device can be fabricated at high yields.
摘要翻译：一种半导体器件，包括：形成在基底基板10上方的第一绝缘膜60; 形成在第一绝缘膜上并且具有与第一绝缘膜不同的蚀刻特性的第二绝缘膜61; 以及电容器79，其包括形成在第二绝缘膜上的存储电极68，从其突出形成有从第二绝缘膜的侧表面向下延伸的存储电极。存储电极的下端部分地形成在蚀刻停止膜的下方，由此通过蚀刻停止膜固定存储电极。因此，防止了诸如湿蚀刻等处理的存储电极的剥离。可以以高产率制造半导体器件。

7. 发明授权

US08080852B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US08080852B2
公开(公告)日：2011-12-20
申请号：US12965422
申请日：2010-12-10
申请人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

8. 发明申请

US20110111567A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110111567A1
公开(公告)日：2011-05-12
申请号：US13010416
申请日：2011-01-20
申请人： Tomohiko TSUTSUMI , Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
发明人： Tomohiko TSUTSUMI , Taiji EMA , Hideyuki KOJIMA , Toru ANEZAKI
IPC分类号： H01L21/8234
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
摘要翻译：半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

9. 发明授权

US07936579B2 Semiconductor memory device and semiconductor device group 有权
标题翻译：半导体存储器件和半导体器件组
公开(公告)号：US07936579B2
公开(公告)日：2011-05-03
申请号：US12792115
申请日：2010-06-02
申请人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
发明人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
IPC分类号： G11C5/06
CPC分类号： H01L27/1104 , G11C5/063 , G11C11/412 , H01L27/11 , Y10S257/903
摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.
摘要翻译：半导体器件包括第一CMOS反相器，第二CMOS反相器，第一传输晶体管和第二传输晶体管，其中第一和第二传输晶体管分别形成在由器件隔离区限定在半导体器件上的第一和第二器件区域中，为了彼此并联延伸，第一传输晶体管在第一器件区域上的第一位接触区域处与第一位线接触，第二传输晶体管在第二位线处与第二位线接触，第二位线在第二位接触区域处器件区域，其中第一位接触区域形成在第一器件区域中，使得所述位接触区域的中心朝向第二器件区域偏移，并且其中第二位接触区域形成在第二器件区域中，使得第二位接触区域的中心朝向第一器件区域偏移。

10. 发明授权

US07888740B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07888740B2
公开(公告)日：2011-02-15
申请号：US11944073
申请日：2007-11-21
申请人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
摘要翻译：半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

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