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1. 发明授权

US07972958B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07972958B2
公开(公告)日：2011-07-05
申请号：US12385982
申请日：2009-04-27
申请人： Jung-hoon Lee , Hong-jae Shin , Seo-woo Nam , Sae-il Son , Sang-doo Kim , Jung-deog Lee , Sang-wook Kwon
发明人： Jung-hoon Lee , Hong-jae Shin , Seo-woo Nam , Sae-il Son , Sang-doo Kim , Jung-deog Lee , Sang-wook Kwon
IPC分类号： H01L21/44
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/7843
摘要： Provided is a method of fabricating a semiconductor device including a dual silicide process. The method may include sequentially siliciding and stressing a first MOS region, and sequentially siliciding and stressing a second MOS region after siliciding and stressing the first MOS region, the second MOS region being a different type than the first MOS region.
摘要翻译：提供一种制造包括双重硅化物工艺的半导体器件的方法。该方法可以包括顺序硅化和应力第一MOS区，并且在硅化和应力第一MOS区之后，依次硅化和应力第二MOS区，第二MOS区是与第一MOS区不同的类型。

2. 发明申请

US20090280645A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090280645A1
公开(公告)日：2009-11-12
申请号：US12385982
申请日：2009-04-27
申请人： Jung-hoon Lee , Hong-jae Shin , Seo-woo Nam , Sae-il Son , Sang-doo Kim , Jung-deog Lee , Sang-wook Kwon
发明人： Jung-hoon Lee , Hong-jae Shin , Seo-woo Nam , Sae-il Son , Sang-doo Kim , Jung-deog Lee , Sang-wook Kwon
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/7843
摘要： Provided is a method of fabricating a semiconductor device including a dual suicide process. The method may include sequentially siliciding and stressing a first MOS region, and sequentially siliciding and stressing a second MOS region after siliciding and stressing the first MOS region, the second MOS region being a different type than the first MOS region.
摘要翻译：提供一种制造包括双重自杀处理的半导体器件的方法。该方法可以包括顺序硅化和应力第一MOS区，并且在硅化和应力第一MOS区之后，依次硅化和应力第二MOS区，第二MOS区是与第一MOS区不同的类型。

3. 发明申请

US20080067612A1 Semiconductor Device Including Nickel Alloy Silicide Layer Having Uniform Thickness and Method of Manufacturing the Same 审中-公开
标题翻译：包括具有均匀厚度的镍合金硅化物层的半导体器件及其制造方法
公开(公告)号：US20080067612A1
公开(公告)日：2008-03-20
申请号：US11775089
申请日：2007-07-09
申请人： Sun Jung Lee , Bong-seok Suh , Hong-jae Shin , Kee-young Jun , Jung-hoon Lee
发明人： Sun Jung Lee , Bong-seok Suh , Hong-jae Shin , Kee-young Jun , Jung-hoon Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/324 , H01L21/28052 , H01L21/28518 , H01L21/288 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： A semiconductor device including a nickel alloy silicide layer having a uniform thickness includes isolation regions formed in a substrate, gate electrodes respectively formed on the substrate between the isolation regions, source/drain regions respectively formed between the gate electrodes and the isolation regions, spacers formed on lateral surfaces of the gate electrodes, and a nickel alloy silicide layer formed on upper portions of the source/drain regions.
摘要翻译：包括具有均匀厚度的镍合金硅化物层的半导体器件包括形成在衬底中的隔离区域，分别形成在隔离区域之间的衬底上的栅电极，分别形成在栅极电极和隔离区域之间的源极/漏极区域，形成间隔物在栅电极的侧表面上形成的镍合金硅化物层和形成在源/漏区上部的镍合金硅化物层。

4. 发明申请

US20070298600A1 Method of Fabricating Semiconductor Device and Semiconductor Device Fabricated Thereby 审中-公开
标题翻译：由此制造半导体器件和半导体器件的方法
公开(公告)号：US20070298600A1
公开(公告)日：2007-12-27
申请号：US11425841
申请日：2006-06-22
申请人： Bong-seok Suh , Hong-jae Shin , Sun-jung Lee , Min-chul Sun , Jung-hoon Lee
发明人： Bong-seok Suh , Hong-jae Shin , Sun-jung Lee , Min-chul Sun , Jung-hoon Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/76846
摘要： A method of fabricating a semiconductor device and a semiconductor device fabricated thereby. The method of fabricating the semiconductor device includes forming gate electrodes on a semiconductor substrate; forming source/drain regions within the semiconductor substrate so as to be located at both sides of each of the gate electrodes; forming a nickel silicide layer on surfaces of the gate electrodes and the source/drain regions by evaporating nickel or nickel alloy on the semiconductor substrate formed with the gate electrodes and the source/drain regions and then performing a thermal process on the nickel or the nickel alloy; forming an interlayer insulating layer, which is formed with contact holes through which a surface of the nickel silicide layer is exposed, on a surface obtained after the above processes have been performed; forming an ohmic layer by evaporating a refractory metal conformably along the contact holes, the refractory metal being converted to silicide at a temperature of 500° C. or more; forming a diffusion barrier on the ohmic layer conformably along the contact holes; and forming a metal layer by burying a metal material within the contact holes.
摘要翻译：一种制造半导体器件的方法及其制造的半导体器件。制造半导体器件的方法包括在半导体衬底上形成栅电极; 在半导体衬底内形成源/漏区，以便位于每个栅电极的两侧; 通过在形成有栅电极和源极/漏极区域的半导体衬底上蒸发镍或镍合金，然后在镍或镍上进行热处理，在栅电极和源/漏区的表面上形成硅化镍层合金; 形成层间绝缘层，所述层间绝缘层在进行上述处理后得到的表面上形成有暴露所述镍硅化物层的表面的接触孔; 通过沿着接触孔顺应蒸发难熔金属形成欧姆层，难熔金属在500℃或更高的温度下转化为硅化物; 在欧姆层上沿着接触孔顺应地形成扩散阻挡层; 以及通过在接触孔内埋入金属材料来形成金属层。

5. 发明授权

US08184473B2 Nanowire memory device and method of manufacturing the same 有权
公开(公告)号：US08184473B2
公开(公告)日：2012-05-22
申请号：US12872835
申请日：2010-08-31
申请人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
发明人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
IPC分类号： G11C11/50
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/16 , H01L51/0048 , Y10S977/943
摘要： A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.

6. 发明申请

US20070019479A1 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US20070019479A1
公开(公告)日：2007-01-25
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： G11C7/10
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

7. 发明授权

US07985646B2 Method of fabricating nanowire memory device and system of controlling nanowire formation used in the same 有权
标题翻译：制造纳米线存储器件的方法及其中使用的纳米线形成控制系统
公开(公告)号：US07985646B2
公开(公告)日：2011-07-26
申请号：US11712990
申请日：2007-03-02
申请人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
发明人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
IPC分类号： G11C11/50
CPC分类号： H01L27/10 , B82Y10/00
摘要： A method of fabricating a nanowire memory device, and a system of controlling nanowire formation used in the same method are provided. In the method of fabricating a nanowire memory device which includes a substrate; an electrode formed on the substrate and insulated from the substrate; and a nanowire having its one end connected with the electrode and formed at a given length, the method comprises: forming an electrode and a dummy electrode to be paired with the electrode on the substrate; forming the nanowire between the electrode and the dummy electrode while measuring a current flowing between the electrode and the dummy electrode, and cutting power applied between the electrode and the dummy electrode when the current measured is a given value; and removing the dummy electrode.
摘要翻译：提供了制造纳米线存储器件的方法，以及以相同方法使用的控制纳米线形成的系统。在制造包括衬底的纳米线存储器件的方法中; 形成在基板上并与基板绝缘的电极; 和一个纳米线，其一端与电极连接并以给定的长度形成，该方法包括：在基片上形成与电极配对的电极和虚拟电极; 在测量电极和虚拟电极之间的电流的同时，在电极和虚拟电极之间形成纳米线，并且当所测量的电流为给定值时，切割施加在电极和虚拟电极之间的功率; 并去除虚拟电极。

8. 发明申请

US20080315285A1 Non-volatile memory devices and methods of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080315285A1
公开(公告)日：2008-12-25
申请号：US12071452
申请日：2008-02-21
申请人： Tae-hee Lee , Jae-woong Hyun , Ju-hee Park , In-kyeong Yoo , Yoon-dong Park , Won-joo Kim , Jung-hoon Lee
发明人： Tae-hee Lee , Jae-woong Hyun , Ju-hee Park , In-kyeong Yoo , Yoon-dong Park , Won-joo Kim , Jung-hoon Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode.
摘要翻译：提供非易失性存储器件及其制造方法。非易失性存储器件可以包括具有从半导体衬底延伸并且彼此相对的一对侧壁沟道区的半导体衬底，以及在该对侧壁沟道区之间并从半导体衬底突出的浮置栅电极。控制栅电极可以形成在半导体衬底和浮栅电极的一部分上。

9. 发明授权

US08576490B2 Changeable liquid lens array and method of manufacturing the same 有权
标题翻译：可变液体透镜阵列及其制造方法
公开(公告)号：US08576490B2
公开(公告)日：2013-11-05
申请号：US13278625
申请日：2011-10-21
申请人： Jung-mok Bae , Hong-seok Lee , Hoon Song , Yong-joo Kwon , Jung-hoon Lee , Seung-yul Choi
发明人： Jung-mok Bae , Hong-seok Lee , Hoon Song , Yong-joo Kwon , Jung-hoon Lee , Seung-yul Choi
IPC分类号： G02B27/10 , G02B3/12 , G02F1/01 , G02B26/02
CPC分类号： G02B26/005 , G02B3/0056 , G02B3/14
摘要： A changeable liquid lens array and a method of manufacturing the same. The changeable liquid lens array includes a substrate, a plurality of partition walls arrayed on the substrate and having a fluid travel path, cells defined by the plurality of partition walls, a first fluid comprised in the cells, a second fluid arranged on the first fluid, a first electrode arranged on at least one side surface of each of the partition walls, and a second electrode disposed to be separate from the partition walls. A shape of an interface between the first fluid and the second fluid changes based on a voltage that is applied to the first electrode and the second electrode.
摘要翻译：一种可变液晶透镜阵列及其制造方法。可变液体透镜阵列包括基板，排列在基板上并具有流体行进路径的多个分隔壁，由多个分隔壁限定的单元，包含在单元中的第一流体，布置在第一流体上的第二流体，布置在每个分隔壁的至少一个侧表面上的第一电极和设置成与分隔壁分离的第二电极。基于施加到第一电极和第二电极的电压，第一流体和第二流体之间的界面的形状发生变化。

10. 发明授权

US07679960B2 Non-volatile memory device and method of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07679960B2
公开(公告)日：2010-03-16
申请号：US11980358
申请日：2007-10-31
申请人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-Iae Cho , Jung-hoon Lee , Seung-hwan Song
发明人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-Iae Cho , Jung-hoon Lee , Seung-hwan Song
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1203
摘要： A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor layer, and the plurality of upper control gate electrodes and the plurality of lower control gate electrodes are disposed alternately. A plurality of upper charge storage layers are interposed between the semiconductor layer and the upper control gate electrodes. A plurality of lower charge storage layers are interposed between the semiconductor layer and the lower control gate electrodes.
摘要翻译：提供高度集成的非易失性存储器件和操作非易失性存储器件的方法。非易失性存储器件包括半导体层。多个上控制栅电极设置在半导体层的上方。多个下部控制栅电极配置在半导体层的下方，多个上部控制栅极电极和多个下部控制栅极电极交替配置。多个上电荷存储层插入在半导体层和上控制栅电极之间。多个下电荷存储层插入在半导体层和下控制栅电极之间。

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