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1. 发明授权

US07037828B2 Semiconductor device having a capping layer including cobalt and method of fabricating the same 失效
标题翻译：具有包含钴的覆盖层的半导体器件及其制造方法
公开(公告)号：US07037828B2
公开(公告)日：2006-05-02
申请号：US10916303
申请日：2004-08-10
申请人： Jung-Wook Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
发明人： Jung-Wook Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
IPC分类号： H01L21/44
CPC分类号： H01L23/485 , H01L21/76841 , H01L21/7685 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.
摘要翻译：半导体器件及其制造方法包括钴作为覆盖层。半导体器件的互连结构具有改善的通孔电阻。在半导体器件中，使用单个钴层或包含钴层和氮化钛层的复合膜作为金属层的覆盖层。

2. 发明申请

US20050046027A1 Semiconductor device having a capping layer including cobalt and method of fabricating the same 失效
标题翻译：具有包含钴的覆盖层的半导体器件及其制造方法
公开(公告)号：US20050046027A1
公开(公告)日：2005-03-03
申请号：US10916303
申请日：2004-08-10
申请人： Jung-Wook Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
发明人： Jung-Wook Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
IPC分类号： H01L21/28 , H01L21/768 , H01L23/485 , H01L21/4763 , H01L29/40
CPC分类号： H01L23/485 , H01L21/76841 , H01L21/7685 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.
摘要翻译：半导体器件及其制造方法包括钴作为覆盖层。半导体器件的互连结构具有改善的通孔电阻。在半导体器件中，使用单个钴层或包含钴层和氮化钛层的复合膜作为金属层的覆盖层。

3. 发明申请

US20060145269A1 Semiconductor device having a capping layer including cobalt and method of fabricating the same 审中-公开
公开(公告)号：US20060145269A1
公开(公告)日：2006-07-06
申请号：US11365063
申请日：2006-02-28
申请人： Jung-Wook Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
发明人： Jung-Wook Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
IPC分类号： H01L29/94 , H01L23/48
CPC分类号： H01L23/485 , H01L21/76841 , H01L21/7685 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.

4. 发明申请

US20060281289A1 Method of forming polycide layer and method of manufacturing semiconductor device having polycide layer 审中-公开
标题翻译：形成聚酰亚胺层的方法和制造具有多晶硅化物层的半导体器件的方法
公开(公告)号：US20060281289A1
公开(公告)日：2006-12-14
申请号：US11446981
申请日：2006-06-06
申请人： Young-Cheon Kim , Chul Hwangbo , Rak-Hwan Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
发明人： Young-Cheon Kim , Chul Hwangbo , Rak-Hwan Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/26513 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4933 , H01L29/6659 , H01L29/7833
摘要： In a method of forming a polycide layer and method of manufacturing a semiconductor device having the polycide layer, the method may include forming a preliminary polysilicon layer doped with first type impurities on a substrate having a first region and a second region, implanting second type of impurities into a portion of the preliminary polysilicon layer on the second region, heat treating the preliminary polysilicon layer to electrically activate the impurities, removing a portion of an upper surface of the heat treated preliminary polysilicon layer to obtain a polysilicon layer, forming a metal silicide layer on the polysilicon layer, and patterning the polysilicon layer and the metal silicide layer to form a first type gate electrode on the first region and to form a second type gate electrode on the second region.
摘要翻译：在形成多晶硅化合物层的方法和制造具有多晶硅化物层的半导体器件的方法中，该方法可以包括在具有第一区域和第二区域的衬底上形成掺杂有第一类型杂质的初步多晶硅层，杂质进入第二区域的初步多晶硅层的一部分，热处理初步多晶硅层以电激活杂质，去除热处理的初步多晶硅层的上表面的一部分以获得多晶硅层，形成金属硅化物并且在所述第一区域上形成所述多晶硅层和所述金属硅化物层以形成第一类型的栅电极，并在所述第二区域上形成第二类型的栅电极。

5. 发明授权

US07311109B2 Method for cleaning a processing chamber and method for manufacturing a semiconductor device 有权
标题翻译：用于清洁处理室的方法和用于制造半导体器件的方法
公开(公告)号：US07311109B2
公开(公告)日：2007-12-25
申请号：US10606512
申请日：2003-06-26
申请人： Jung-wook Kim , Hyeon-Deok Lee , Jin-Gi Hong , Ji-Soon Park , Eung-Joon Lee
发明人： Jung-wook Kim , Hyeon-Deok Lee , Jin-Gi Hong , Ji-Soon Park , Eung-Joon Lee
IPC分类号： B08B9/00 , H01L21/00
CPC分类号： C23C16/4405 , C23C16/0245 , H01L21/02063 , H01L21/76814 , Y10S438/905
摘要： A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.
摘要翻译：一种清洗处理室的方法，并且利用包含氢气的第一气体的等离子体从处理室中的基板上除去杂质来制造半导体器件。在从处理室移除基板之后，用非氢气的第二气体的等离子体蚀刻处理室。因此，可以提高蚀刻选择性，并且防止颗粒在衬底上沉积和/或形成。

6. 发明授权

US07199019B2 Method for forming tungsten contact plug 有权
标题翻译：形成钨接触塞的方法
公开(公告)号：US07199019B2
公开(公告)日：2007-04-03
申请号：US11002682
申请日：2004-12-03
申请人： Ji-Soon Park , Hyun-Seok Lim , Eung-Joon Lee , Jung-Wook Kim
发明人： Ji-Soon Park , Hyun-Seok Lim , Eung-Joon Lee , Jung-Wook Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/28562 , H01L21/76843 , H01L21/76844 , H01L21/76876 , H01L21/76879 , H01L2221/1089
摘要： A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.
摘要翻译：一种用于形成半导体器件的钨接触插塞的方法，包括在半导体衬底上沉积绝缘层，蚀刻绝缘层以形成接触孔，其暴露导电区域，在具有接触孔的半导体衬底上形成阻挡层改变绝缘层上的阻挡层的一部分和接触保持部中阻挡层的部分的特性，使得绝缘层上的阻挡层与接触孔中的阻挡层之间的特性不同，沉积钨在阻挡层上形成钨接触塞的层，以及从绝缘层的上部去除钨层以使半导体器件平坦化。

7. 发明申请

US20120120728A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20120120728A1
公开(公告)日：2012-05-17
申请号：US13191581
申请日：2011-07-27
申请人： Su-Kyoung KIM , Gil-Heyun Choi , Jong-Myeong Lee , In-Sun Park , Ji-Soon Park
发明人： Su-Kyoung KIM , Gil-Heyun Choi , Jong-Myeong Lee , In-Sun Park , Ji-Soon Park
IPC分类号： G11C11/34 , H01L21/336 , H01L29/788
CPC分类号： H01L29/7926 , G11C5/063 , G11C16/0483 , H01L27/11582
摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.
摘要翻译：提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅电极和与衬底垂直交替堆叠的多个层间电介质层，以及形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

8. 发明授权

US06797618B2 Method for forming silicide film of a semiconductor device 失效
标题翻译：半导体器件的硅化物膜的形成方法
公开(公告)号：US06797618B2
公开(公告)日：2004-09-28
申请号：US10630570
申请日：2003-07-29
申请人： Eung-Joon Lee , In-Sun Park , Ji-Soon Park
发明人： Eung-Joon Lee , In-Sun Park , Ji-Soon Park
IPC分类号： H01L2144
CPC分类号： H01L21/0206 , H01L21/02063 , H01L21/28052 , H01L21/28518 , H01L21/324 , H01L29/665 , Y10S438/906 , Y10S438/963
摘要： A conductive pattern having a surface including silicon is formed on a substrate of a semiconductor device and a conduction region having a surface including silicon is formed in the substrate. A radio frequency etching process is performed ex-situ to remove impurities from a resultant structure and to improve surface characteristics of the conduction region. Residues generated during the radio frequency etching process are removed from the conductive pattern and the conduction region by a cleaning process. A metal film is formed on the conductive pattern and the conduction region. A silicide film is formed on the conductive pattern and the conduction region by reacting metal of the metal film and silicon in the conductive pattern and the conduction region. With a radio frequency sputtering process and a wet cleaning process, a metal silicide film having a uniform phase may be stably formed.
摘要翻译：在半导体器件的衬底上形成具有包括硅的表面的导电图案，并且在衬底中形成具有包括硅的表面的导电区域。非原位地进行射频蚀刻处理以从所得结构中去除杂质并改善导电区域的表面特性。在射频蚀刻工艺中产生的残留物通过清洁处理从导电图案和导电区域中去除。在导电图案和导电区域上形成金属膜。通过金属膜的金属和导电图案中的硅和导电区域之间的反应，在导电图案和导电区域上形成硅化物膜。通过射频溅射法和湿式清洗法，可以稳定地形成具有均匀相的金属硅化物膜。

9. 发明授权

US08547747B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08547747B2
公开(公告)日：2013-10-01
申请号：US13191581
申请日：2011-07-27
申请人： Su-Kyoung Kim , Gil-Heyun Choi , Jong-Myeong Lee , In-Sun Park , Ji-Soon Park
发明人： Su-Kyoung Kim , Gil-Heyun Choi , Jong-Myeong Lee , In-Sun Park , Ji-Soon Park
IPC分类号： G11C16/04
CPC分类号： H01L29/7926 , G11C5/063 , G11C16/0483 , H01L27/11582
摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.
摘要翻译：提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅极电极和与衬底垂直交替堆叠的多个层间电介质层，以及形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

10. 发明授权

US08476763B2 Semiconductor device conductive pattern structures including dummy conductive patterns 有权
标题翻译：包括虚拟导电图案的半导体器件导电图案结构
公开(公告)号：US08476763B2
公开(公告)日：2013-07-02
申请号：US13237514
申请日：2011-09-20
申请人： Hei-Seung Kim , In-Sun Park , Gil-Heyun Choi , Ji-Soon Park , Jong-Myeong Lee , Jong-Won Hong
发明人： Hei-Seung Kim , In-Sun Park , Gil-Heyun Choi , Ji-Soon Park , Jong-Myeong Lee , Jong-Won Hong
IPC分类号： H01L23/48 , H01L21/4763 , H01L27/10 , H01L21/3205 , H01L21/768 , G06F17/50
CPC分类号： H01L21/2885 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L21/76838 , H01L21/76877 , H01L23/522 , H01L23/53238 , H01L27/0207 , H01L27/11529 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.
摘要翻译：形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。第二沟槽在电池块的中间部分具有断开的形状。在绝缘中间层上形成种子铜层。第一，第二和第三沟槽的内部部分用铜层电镀。抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。还描述了相关的导电图案结构。

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