专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09287270B2 Semiconductor device and fabricating method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09287270B2
公开(公告)日：2016-03-15
申请号：US14279301
申请日：2014-05-15
申请人： Jung-Hwan Oh , Hyun-Jun Kim , Jong-Bom Seo , Ki-Vin Im , Han-Jin Lim
发明人： Jung-Hwan Oh , Hyun-Jun Kim , Jong-Bom Seo , Ki-Vin Im , Han-Jin Lim
IPC分类号： H01L27/108 , H01L49/02
CPC分类号： H01L27/10805 , H01L27/10808 , H01L27/1085 , H01L28/91
摘要： Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.
摘要翻译：提供一种半导体器件及其制造方法。半导体器件包括具有圆柱形状的存储电极，形成在存储电极上的电介质膜和形成在电介质膜上的平板电极，其中该平板电极包括一个第一半导体化合物层和第二半导体化合物层，另一方面，第一半导体化合物层的结晶度与第二半导体化合物层的结晶度不同。

2. 发明授权

US09184227B1 Methods of manufacturing semiconductor devices having self-aligned contact pads 有权
标题翻译：制造具有自对准接触焊盘的半导体器件的方法
公开(公告)号：US09184227B1
公开(公告)日：2015-11-10
申请号：US14529500
申请日：2014-10-31
申请人： Young-Kuk Kim , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
发明人： Young-Kuk Kim , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
IPC分类号： H01L21/336 , H01L49/02 , H01L21/8234
CPC分类号： H01L27/10823 , H01L21/823437 , H01L21/823475 , H01L27/10808 , H01L27/10855 , H01L27/10885 , H01L28/60 , H01L29/4236 , H01L29/42364 , H01L29/7827
摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.
摘要翻译：半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极，所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽，相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构线路和相应接触焊盘上的电容器的下电极。

3. 发明授权

US09240414B1 Semiconductor devices having self-aligned contact pads 有权
标题翻译：具有自对准接触焊盘的半导体器件
公开(公告)号：US09240414B1
公开(公告)日：2016-01-19
申请号：US14875396
申请日：2015-10-05
申请人： Young-Kuk Kim , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
发明人： Young-Kuk Kim , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
IPC分类号： H01L21/336 , H01L27/108 , H01L29/78 , H01L29/423
CPC分类号： H01L27/10823 , H01L21/823437 , H01L21/823475 , H01L27/10808 , H01L27/10855 , H01L27/10885 , H01L28/60 , H01L29/4236 , H01L29/42364 , H01L29/7827
摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.
摘要翻译：半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极，所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽，相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构线路和相应接触焊盘上的电容器的下电极。

4. 发明申请

US20150311276A1 SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED CONTACT PADS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：具有自对准接触垫的半导体器件及其制造方法
公开(公告)号：US20150311276A1
公开(公告)日：2015-10-29
申请号：US14529500
申请日：2014-10-31
申请人： YOUNG-KUK KIM , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
发明人： YOUNG-KUK KIM , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
IPC分类号： H01L49/02 , H01L21/8234
CPC分类号： H01L27/10823 , H01L21/823437 , H01L21/823475 , H01L27/10808 , H01L27/10855 , H01L27/10885 , H01L28/60 , H01L29/4236 , H01L29/42364 , H01L29/7827
摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.
摘要翻译：半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极，所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽，相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构线路和相应接触焊盘上的电容器的下电极。

5. 发明申请

US20140327062A1 ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS 审中-公开
标题翻译：包括氧化物介质和界面层的电子器件
公开(公告)号：US20140327062A1
公开(公告)日：2014-11-06
申请号：US14073354
申请日：2013-11-06
申请人： Ki-Yeon PARK , Hyun-Jun Kim , Se-Hyoung Ahn , Young-Geun Park , Ki-Vin Im
发明人： Ki-Yeon PARK , Hyun-Jun Kim , Se-Hyoung Ahn , Young-Geun Park , Ki-Vin Im
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/60 , H01L27/10808 , H01L27/1085 , H01L28/40 , H01L29/4236 , H01L29/513 , H01L29/517
摘要： An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.
摘要翻译：电子器件可以包括衬底，衬底上的氧化物介电层，氧化物介电层上的界面层和界面层上的电极。氧化物介电层可以包括在第一和第二氧化锆层之间的氧化铝层。界面层可以具有第一形成焓，并且氧化物介电层可以在衬底和界面层之间。电极可具有比第一形成焓高的第二形成焓，并且界面层可以在氧化物介电层和电极之间。

6. 发明申请

US20080054244A1 PHASE CHANGE MEMORY DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20080054244A1
公开(公告)日：2008-03-06
申请号：US11697230
申请日：2007-04-05
申请人： Jin-Il Lee , Ji-Eun Lim , Hye-Young Park , Sung-Lae Cho , Eun-Ae Chung , Ki-Vin Im , Byoung-Jae Bae , Young-Lim Park
发明人： Jin-Il Lee , Ji-Eun Lim , Hye-Young Park , Sung-Lae Cho , Eun-Ae Chung , Ki-Vin Im , Byoung-Jae Bae , Young-Lim Park
IPC分类号： H01L29/02
CPC分类号： H01L45/1616 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： In one embodiment, a phase change memory device includes an insulation structure over a substrate. The insulation structure ahs an opening defined therethrough. A first layer pattern is formed on sidewalls and a bottom of the opening. A second layer pattern is formed on the first layer pattern and substantially fills the opening.
摘要翻译：在一个实施例中，相变存储器件包括在衬底上的绝缘结构。绝缘结构是通过其限定的开口。第一层图案形成在开口的侧壁和底部上。在第一层图案上形成第二层图案并且基本上填充开口。

7. 发明授权

US07094712B2 High performance MIS capacitor with HfO2 dielectric 失效
标题翻译：具有HfO2电介质的高性能MIS电容器
公开(公告)号：US07094712B2
公开(公告)日：2006-08-22
申请号：US10793818
申请日：2004-03-08
申请人： Ki-Vin Im , Ki-Yeon Park , Jae-Hyun Yeo , In-Sung Park , Seung-Hwan Lee , Young-Sun Kim , Sung-Tae Kim
发明人： Ki-Vin Im , Ki-Yeon Park , Jae-Hyun Yeo , In-Sung Park , Seung-Hwan Lee , Young-Sun Kim , Sung-Tae Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02181 , H01L21/022 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Disclosed is a method for forming metal oxide dielectric layers, more particularly HfO2 dielectric layers, using an atomic layer deposition (ALD) method in which a series of thin intermediate layers are formed and treated with one or more oxidizers and nitrogents before the next intermediate layer is formed on the substrate. The intermediate oxidation treatments reduce the number of organic contaminants incorporated into the metal oxide layer from the organometallic precursors to produce a dielectric layer having improved current leakage characteristics. The dielectric layers formed in this manner remain susceptible to crystallization if exposed to temperatures much above 550° C., so subsequent semiconductor manufacturing processes should be modified or eliminated to avoid such temperatures or limit the duration at such temperatures to maintain the performance of the dielectric materials.
摘要翻译：公开了一种使用原子层沉积（ALD）方法形成金属氧化物电介质层，更具体地是HfO 2 电介质层的方法，其中形成一系列薄的中间层并用一个或多个在下一个中间层之前形成氧化剂和氮。中间氧化处理减少了从有机金属前体引入到金属氧化物层中的有机污染物的数量，以产生具有改善的电流泄漏特性的电介质层。如果暴露在高于550℃的温度下，以这种方式形成的电介质层仍然易于结晶，因此随后的半导体制造工艺应当被修改或消除以避免这种温度或限制在这样的温度下的持续时间以保持电介质的性能材料

8. 发明授权

US06897106B2 Capacitor of semiconductor memory device that has composite Al2O3/HfO2 dielectric layer and method of manufacturing the same 失效
标题翻译：具有复合Al2O3 / HfO2电介质层的半导体存储器件的电容器及其制造方法
公开(公告)号：US06897106B2
公开(公告)日：2005-05-24
申请号：US10713577
申请日：2003-11-12
申请人： Ki-Yeon Park , Sung-Tae Kim , Young-Sun Kim , In-Sung Park , Jae-Hyun Yeo , Ki-Vin Im
发明人： Ki-Yeon Park , Sung-Tae Kim , Young-Sun Kim , In-Sung Park , Jae-Hyun Yeo , Ki-Vin Im
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/40 , H01L21/3141 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L28/56 , H01L28/65 , H01L28/75
摘要： A semiconductor memory device that includes a composite Al2O3/HfO2 dielectric layer with a layer thickness ratio greater than or equal to 1, and a method of manufacturing the capacitor are provided. The capacitor includes a lower electrode, a composite dielectric layer including an Al2O3 dielectric layer and an HfO2 dielectric layer sequentially formed on the lower electrode, the Al2O3 dielectric layer having a thickness greater than or equal to the HfO2 dielectric layer, and an upper electrode formed on the composite dielectric layer. The Al2O3 dielectric layer has a thickness of 30-60 Å. The HfO2 dielectric layer has a thickness of 40 Å or less.
摘要翻译：一种半导体存储器件，其包括层厚度比大于或等于1的复合Al 2 O 3 / HfO 2 电介质层，并提供一种制造该电容器的方法。电容器包括下电极，复合电介质层，其包括依次形成在其上的Al 2 O 3 3电介质层和HfO 2 N 2介电层下电极，具有大于或等于HfO 2 2电介质层的厚度的Al 2 O 3 3 电介质层，以及形成的上电极在复合介电层上。 Al 2 O 3介电层具有30-60埃的厚度。 HfO 2 2介电层的厚度为40以下。

9. 发明申请

US20050087791A1 Capacitor of semiconductor memory device that has composite A12O3/HfO2 dielectric layer and method of manufacturing the same 审中-公开
标题翻译：具有复合A12O3 / HfO2介电层的半导体存储器件的电容器及其制造方法
公开(公告)号：US20050087791A1
公开(公告)日：2005-04-28
申请号：US11009198
申请日：2004-12-08
申请人： Ki-Yeon Park , Sung-Tao Kim , Young-Sun Kim , In-Sung Park , Jae-Hyun Yeo , Ki-Vin Im
发明人： Ki-Yeon Park , Sung-Tao Kim , Young-Sun Kim , In-Sung Park , Jae-Hyun Yeo , Ki-Vin Im
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/40 , H01L21/3141 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L28/56 , H01L28/65 , H01L28/75
摘要： A semiconductor memory device that includes a composite Al2O3HfO2 dielectric layer with a layer thickness ratio greater than or equal to 1, and a method of manufacturing the capacitor are provided. The capacitor includes a lower electrode, a composite dielectric layer including an Al2O3 dielectric layer and an HfO2 dielectric layer sequentially formed on the lower electrode, the Al2O3 dielectric layer having a thickness greater than or equal to the HfO2 dielectric layer, and an upper electrode formed on the composite dielectric layer. The Al2O3 dielectric layer has a thickness of 30-60 Å. The HfO2 dielectric layer has a thickness of 40 Å or less.
摘要翻译：一种半导体存储器件，其包括层厚度比大于或等于1的复合Al 2 O 3 HfO 2 电介质层，以及提供了制造电容器的方法。电容器包括下电极，复合电介质层，其包括依次形成在其上的Al 2 O 3 3介电层和HfO 2 O 3介电层下电极，具有大于或等于HfO 2 2电介质层的厚度的Al 2 O 3 3 电介质层，以及形成的上电极在复合介电层上。 Al 2 O 3介电层具有30-60埃的厚度。 HfO 2 2介电层的厚度为40以下。

10. 发明授权

US08394201B2 Atomic layer deposition apparatus 有权
公开(公告)号：US08394201B2
公开(公告)日：2013-03-12
申请号：US12356999
申请日：2009-01-21
申请人： Ki-Hyun Kim , Ki-Vin Im , Hoon-Sang Choi , Moon-Hyeong Han
发明人： Ki-Hyun Kim , Ki-Vin Im , Hoon-Sang Choi , Moon-Hyeong Han
IPC分类号： C23C16/455 , C23C16/46 , C23F1/00 , H01L21/306 , C23C16/06 , C23C16/22
CPC分类号： H01L21/30 , C23C16/45546 , C23C16/45551 , C23C16/45578
摘要： An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式