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1. 发明授权

US09184227B1 Methods of manufacturing semiconductor devices having self-aligned contact pads 有权
标题翻译：制造具有自对准接触焊盘的半导体器件的方法
公开(公告)号：US09184227B1
公开(公告)日：2015-11-10
申请号：US14529500
申请日：2014-10-31
申请人： Young-Kuk Kim , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
发明人： Young-Kuk Kim , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
IPC分类号： H01L21/336 , H01L49/02 , H01L21/8234
CPC分类号： H01L27/10823 , H01L21/823437 , H01L21/823475 , H01L27/10808 , H01L27/10855 , H01L27/10885 , H01L28/60 , H01L29/4236 , H01L29/42364 , H01L29/7827
摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.
摘要翻译：半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极，所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽，相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构线路和相应接触焊盘上的电容器的下电极。

2. 发明授权

US09240414B1 Semiconductor devices having self-aligned contact pads 有权
标题翻译：具有自对准接触焊盘的半导体器件
公开(公告)号：US09240414B1
公开(公告)日：2016-01-19
申请号：US14875396
申请日：2015-10-05
申请人： Young-Kuk Kim , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
发明人： Young-Kuk Kim , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
IPC分类号： H01L21/336 , H01L27/108 , H01L29/78 , H01L29/423
CPC分类号： H01L27/10823 , H01L21/823437 , H01L21/823475 , H01L27/10808 , H01L27/10855 , H01L27/10885 , H01L28/60 , H01L29/4236 , H01L29/42364 , H01L29/7827
摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.
摘要翻译：半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极，所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽，相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构线路和相应接触焊盘上的电容器的下电极。

3. 发明申请

US20150311276A1 SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED CONTACT PADS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：具有自对准接触垫的半导体器件及其制造方法
公开(公告)号：US20150311276A1
公开(公告)日：2015-10-29
申请号：US14529500
申请日：2014-10-31
申请人： YOUNG-KUK KIM , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
发明人： YOUNG-KUK KIM , Ki-Vin Im , Han-Jin Lim , In-Seak Hwang
IPC分类号： H01L49/02 , H01L21/8234
CPC分类号： H01L27/10823 , H01L21/823437 , H01L21/823475 , H01L27/10808 , H01L27/10855 , H01L27/10885 , H01L28/60 , H01L29/4236 , H01L29/42364 , H01L29/7827
摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.
摘要翻译：半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极，所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽，相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构线路和相应接触焊盘上的电容器的下电极。

4. 发明授权

US09287270B2 Semiconductor device and fabricating method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09287270B2
公开(公告)日：2016-03-15
申请号：US14279301
申请日：2014-05-15
申请人： Jung-Hwan Oh , Hyun-Jun Kim , Jong-Bom Seo , Ki-Vin Im , Han-Jin Lim
发明人： Jung-Hwan Oh , Hyun-Jun Kim , Jong-Bom Seo , Ki-Vin Im , Han-Jin Lim
IPC分类号： H01L27/108 , H01L49/02
CPC分类号： H01L27/10805 , H01L27/10808 , H01L27/1085 , H01L28/91
摘要： Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.
摘要翻译：提供一种半导体器件及其制造方法。半导体器件包括具有圆柱形状的存储电极，形成在存储电极上的电介质膜和形成在电介质膜上的平板电极，其中该平板电极包括一个第一半导体化合物层和第二半导体化合物层，另一方面，第一半导体化合物层的结晶度与第二半导体化合物层的结晶度不同。

5. 发明授权

US08481398B2 Method of forming semiconductor device having a capacitor 有权
标题翻译：形成具有电容器的半导体器件的方法
公开(公告)号：US08481398B2
公开(公告)日：2013-07-09
申请号：US12659548
申请日：2010-03-12
申请人： Seung-Sik Chung , Jung-Hee Chung , Young-Jin Kim , Seok-Woo Nam , Han-Jin Lim , Kyoung-Ryul Yoon
发明人： Seung-Sik Chung , Jung-Hee Chung , Young-Jin Kim , Seok-Woo Nam , Han-Jin Lim , Kyoung-Ryul Yoon
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10814 , H01L28/91
摘要： A method of forming a semiconductor device includes forming a lower electrode layer on a substrate, forming a surface oxide layer on the lower electrode layer, partially removing the lower electrode layer to form a lower electrode, removing the surface oxide layer to expose the lower electrode, forming a capacitor dielectric layer on the lower electrode, and forming an upper electrode on the capacitor dielectric layer.
摘要翻译：形成半导体器件的方法包括在衬底上形成下电极层，在下电极层上形成表面氧化层，部分地去除下电极层以形成下电极，去除表面氧化层以暴露下电极在下电极上形成电容器电介质层，并在电容器介电层上形成上电极。

6. 发明申请

US20100240191A1 METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A CAPACITOR 有权
标题翻译：形成具有电容器的半导体器件的方法
公开(公告)号：US20100240191A1
公开(公告)日：2010-09-23
申请号：US12659548
申请日：2010-03-12
申请人： Seung-Sik Chung , Jung-Hee Chung , Young-Jin Kim , Seok-Woo Nam , Han-Jin Lim , Kyoung-Ryul Yoon
发明人： Seung-Sik Chung , Jung-Hee Chung , Young-Jin Kim , Seok-Woo Nam , Han-Jin Lim , Kyoung-Ryul Yoon
IPC分类号： H01L21/02
CPC分类号： H01L27/10852 , H01L27/10814 , H01L28/91
摘要： A method of forming a semiconductor device includes forming a lower electrode layer on a substrate, forming a surface oxide layer on the lower electrode layer, partially removing the lower electrode layer to form a lower electrode, removing the surface oxide layer to expose the lower electrode, forming a capacitor dielectric layer on the lower electrode, and forming an upper electrode on the capacitor dielectric layer.
摘要翻译：形成半导体器件的方法包括在衬底上形成下电极层，在下电极层上形成表面氧化层，部分地去除下电极层以形成下电极，去除表面氧化层以暴露下电极在下电极上形成电容器电介质层，并在电容器介电层上形成上电极。

7. 发明授权

US07722926B2 Organometallic compounds and methods of forming thin films including the use of the same 有权
标题翻译：有机金属化合物和形成薄膜的方法包括使用它们
公开(公告)号：US07722926B2
公开(公告)日：2010-05-25
申请号：US11460485
申请日：2006-07-27
申请人： Kyu-Ho Cho , Seung-Ho Yoo , Byung-Soo Kim , Jae-Sun Jung , Han-Jin Lim , Ki-Chul Kim , Jae-Soon Lim
发明人： Kyu-Ho Cho , Seung-Ho Yoo , Byung-Soo Kim , Jae-Sun Jung , Han-Jin Lim , Ki-Chul Kim , Jae-Soon Lim
IPC分类号： C23C16/00
CPC分类号： C23C16/40 , C07C217/08 , C23C16/403 , C23C16/45525 , C23C16/45553
摘要： The present invention provides organometallic compounds and methods of forming thin films including using the same. The organometallic compounds include a metal and a ligand linked to the metal. The ligand can be represented by the following formula (1): wherein R1 and R2 are each independently hydrogen or an alkyl group. The thin films may be applied to semiconductor structures such as a gate insulation layer of a gate structure and a dielectric layer of a capacitor.
摘要翻译：本发明提供有机金属化合物和形成薄膜的方法，包括使用它们。有机金属化合物包括与金属连接的金属和配体。配体可以由下式（1）表示：其中R 1和R 2各自独立地为氢或烷基。薄膜可以应用于诸如栅极结构的栅极绝缘层和电容器的电介质层的半导体结构。

8. 发明授权

US09202813B2 Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure 有权
标题翻译：电极结构及其制造方法以及包括该电极结构的半导体器件
公开(公告)号：US09202813B2
公开(公告)日：2015-12-01
申请号：US13169348
申请日：2011-06-27
申请人： Dong-kak Lee , Joon Kim , Bong-hyun Kim , Han-Jin Lim
发明人： Dong-kak Lee , Joon Kim , Bong-hyun Kim , Han-Jin Lim
IPC分类号： H01L21/28 , H01L21/311 , H01L27/108 , H01L21/8238 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/28044 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L27/10808 , H01L27/10823 , H01L27/10873 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66575 , H01L29/78
摘要： An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
摘要翻译：公开了电极结构。电极结构包括掺杂有电阻调节杂质的第一多晶硅层; 用于调节晶粒的第二多晶硅层，形成在第一多晶硅层中并掺杂有晶粒调节杂质; 在第一和第二多晶硅层上形成的欧姆金属层; 形成在欧姆金属层上的阻挡金属层; 以及形成在阻挡金属层上的金属层。

9. 发明申请

US20120001267A1 ELECTRODE STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE ELECTRODE STRUCTURE 有权
标题翻译：电极结构，其制造方法以及包括电极结构的半导体器件
公开(公告)号：US20120001267A1
公开(公告)日：2012-01-05
申请号：US13169348
申请日：2011-06-27
申请人： Dong-kak Lee , Joon Kim , Bong-hyun Kim , Han-Jin Lim
发明人： Dong-kak Lee , Joon Kim , Bong-hyun Kim , Han-Jin Lim
IPC分类号： H01L27/092 , H01L29/49 , H01L21/28 , H01L27/088
CPC分类号： H01L27/092 , H01L21/28044 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L27/10808 , H01L27/10823 , H01L27/10873 , H01L29/1037 , H01L29/4236 , H01L29/4238 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66575 , H01L29/78
摘要： An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
摘要翻译：公开了电极结构。电极结构包括掺杂有电阻调节杂质的第一多晶硅层; 用于调节晶粒的第二多晶硅层，形成在第一多晶硅层中并掺杂有晶粒调节杂质; 在第一和第二多晶硅层上形成的欧姆金属层; 形成在欧姆金属层上的阻挡金属层; 以及形成在阻挡金属层上的金属层。

10. 发明申请

US20110124176A1 METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：形成电容器结构的方法和使用其制造半导体器件的方法
公开(公告)号：US20110124176A1
公开(公告)日：2011-05-26
申请号：US12954050
申请日：2010-11-24
申请人： Han-Jin Lim , Jae-Hong Seo , Seok-Woo Nam , Bong-Hyun Kim , Taek-Soo Jeon
发明人： Han-Jin Lim , Jae-Hong Seo , Seok-Woo Nam , Bong-Hyun Kim , Taek-Soo Jeon
IPC分类号： H01L21/02
CPC分类号： H01L28/90 , H01L27/10817 , H01L27/10852
摘要： In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.
摘要翻译：在形成电容器的方法中，在具有插头的绝缘中间层上形成种子阻挡层和牺牲层。通过牺牲层和种子塞子形成开口以露出塞子。在开口的内壁上形成种子。形成了覆盖开口内壁上的种子的下电极。去除牺牲层和种子。电介质层和上电极依次形成在下电极上。

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