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1. 发明授权

US5015886A Programmable sequential-code recognition circuit 失效
标题翻译：可编程顺序码识别电路
公开(公告)号：US5015886A
公开(公告)日：1991-05-14
申请号：US356172
申请日：1989-05-24
申请人： Jung-Dal Choi , Hyung-Kyu Yim , Jae-Young Do , Jin-Ki Kim
发明人： Jung-Dal Choi , Hyung-Kyu Yim , Jae-Young Do , Jin-Ki Kim
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G06F7/02 , G06F11/28 , H03M7/00
CPC分类号： G06F11/28 , G01R31/31701 , G06F7/02
摘要： There is disclosed a programmable sequential code recognition circuit comprising an individual code recognition circuit for recognizing each input code, and a sequence recognition circuit for recognizing the sequency given for individual codes obtained by combination of input signals, so that a specific mode may be selected by the input combination sequentially inputted.
摘要翻译：公开了一种包括用于识别每个输入代码的单独代码识别电路的可编程序序代码识别电路，以及用于识别通过输入信号组合而获得的各个代码给出的顺序的序列识别电路，从而可以通过顺序地输入输入组合。

2. 发明授权

US4983860A Data output buffer for use in semiconductor device 失效
标题翻译：用于半导体器件的数据输出缓冲器
公开(公告)号：US4983860A
公开(公告)日：1991-01-08
申请号：US292342
申请日：1988-12-30
申请人： Hyung-Kyu Yim , Jung-Dal Choi , Woong-Moo Lee
发明人： Hyung-Kyu Yim , Jung-Dal Choi , Woong-Moo Lee
IPC分类号： G11C11/417 , G06F12/08 , G06F13/00 , G11C7/10 , G11C11/409 , H03K19/00 , H03K19/0185 , H03K19/094 , H03K19/096
CPC分类号： G11C7/1057 , G11C7/1051 , H03K19/0013 , H03K19/09429
摘要： A data output buffer being capable of precharging a data bus without increasing its current consumption and without having great dependency upon the process variation, whereby a READ access time of a semiconductor device is considerably reduced and the noise of source supplying voltages (Vcc, Vss) is also controlled to its least possible level in a semiconductor chip. The buffer includes means for minimizing the DC current consumption of a data bus precharge driver by feeding back an electric potential of an I/O port to an input of the precharging driver, and means for making the precharge driver operate during a specified period of time prior to providing the actual data by using an ATD pulse.
摘要翻译：数据输出缓冲器能够在不增加其电流消耗的情况下对数据总线进行预充电，并且不会对工艺变化产生很大的依赖性，从而大大减少了半导体器件的读取访问时间，并且源供给电压（Vcc，Vss）也被控制到其在半导体芯片中的最小可能水平。缓冲器包括用于通过将I / O端口的电位反馈到预充电驱动器的输入来最小化数据总线预充电驱动器的DC电流消耗的装置，以及用于使预充电驱动器在指定时间段内操作的装置在通过使用ATD脉冲提供实际数据之前。

3. 发明授权

US5142541A Error-bit generating circuit for use in a non-volatile semiconductor memory device 失效
标题翻译：在非易失性半导体存储器件中使用的错误产生电路
公开(公告)号：US5142541A
公开(公告)日：1992-08-25
申请号：US292104
申请日：1988-12-30
申请人： Jin-Ki Kim , Hyung-Kyu Yim
发明人： Jin-Ki Kim , Hyung-Kyu Yim
IPC分类号： G11C29/00 , G06F11/10 , G06F11/267 , G11C16/06 , G11C17/00 , G11C29/38 , G11C29/42
CPC分类号： G11C29/02 , G06F11/1008 , G06F11/1076 , G06F11/2215 , G11C29/38 , G06F11/10 , G06F11/1068
摘要： An error-bit generating circuit for use in a nonvolatile semiconductor memory device, particularly in an EEPROM. The circuit is capable of easily checking the deterioration of operational performance in an error checking correction device thereof, by intentionally writing bit-error data into a memory cell thereof. The error-bit generating circuit includes a parity generator for generating specified bits of parity data according to input data received from an input buffer, means for writing into a memory cell array the input data and parity data, means for, after reading out the input data and parity data from the memory cell array, correcting an error-bit among the input data and then providing the corrected data, and an error-bit generator coupled between the input buffer and the memory cell array, for generating an error-bit signal onto a selected bit of the input data in response to a control signal and an address signal.
摘要翻译：一种用于非易失性半导体存储器件，特别是在EEPROM中的误差位产生电路。该电路能够通过有意地将位错误数据写入其存储单元来容易地检查其错误检查校正装置中的操作性能的劣化。错误比特生成电路包括奇偶校验生成器，用于根据从输入缓冲器接收的输入数据产生奇偶校验数据的指定位，用于将输入数据和奇偶校验数据写入存储单元阵列的装置，用于在读出输入来自存储单元阵列的数据和奇偶校验数据，校正输入数据中的错误位，然后提供校正数据，以及耦合在输入缓冲器和存储单元阵列之间的误差位发生器，用于产生误差位信号响应于控制信号和地址信号到输入数据的选定位。

4. 发明授权

US5511022A Depletion mode NAND string electrically erasable programmable semiconductor memory device and method for erasing and programming thereof 失效
标题翻译：耗尽模式NAND串电可擦除可编程半导体存储器件及其擦除和编程方法
公开(公告)号：US5511022A
公开(公告)日：1996-04-23
申请号：US517197
申请日：1995-08-21
申请人： Hyung-Kyu Yim , Woong-Moo Lee
发明人： Hyung-Kyu Yim , Woong-Moo Lee
IPC分类号： G11C17/00 , G11C11/40 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/30 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/30 , H01L29/7883
摘要： A memory string for using in an EEPROM device is provided which has two selection transistors and a plurality of depletion-type floating gate transistors whose drain-source paths are connected in series with each other between two selection transistors. The EEPROM device comprises a memory cell array including a plurality of bit lines arranged in columns and a plurality of memory strings arranged in rows and columns, each of memory strings in the same columns connected between the corresponding bit line and the ground; a row decoder for selecting memory strings in the same row and supplying predetermined voltages to control gates to the floating gate transistors in the selected memory strings according to a program, erase or read operation; a column decoder for coupling the bit lines to a data line according to the operation mode; means for precharging unselected bit lines during the program operation to a predetermined voltage so as to prevent erase of unselected floating gate transistors; a program control circuit connected to the data line for supplying a program voltage to the selected bit line during the program operation; and means for grounding all bit lines during the erase operation.
摘要翻译：提供了一种用于在EEPROM器件中使用的存储器串，其具有两个选择晶体管和多个耗尽型浮栅晶体管，其漏源极路径在两个选择晶体管之间彼此串联连接。 EEPROM装置包括存储单元阵列，其包括排列成列的多个位线和以行和列排列的多个存储器串，每个存储器串在相应的列中连接在相应的位线和地之间; 行解码器，用于根据程序，擦除或读取操作选择同一行中的存储器串并提供预定电压以控制所选存储器串中的浮置栅晶体管的栅极; 列解码器，用于根据操作模式将位线耦合到数据线; 用于在编程操作期间将未选位线预充电至预定电压的装置，以防止未选择的浮置栅极晶体管的擦除; 连接到所述数据线的程序控制电路，用于在所述编程操作期间向所选位线提供编程电压; 以及用于在擦除操作期间使所有位线接地的装置。

5. 发明授权

US4962481A EEPROM device with plurality of memory strings made of floating gate transistors connected in series 失效
标题翻译：具有由串联连接的浮栅晶体管构成的多个存储串的EEPROM器件
公开(公告)号：US4962481A
公开(公告)日：1990-10-09
申请号：US292107
申请日：1988-12-30
申请人： Jung-Hyuk Choi , Soo-Chul Lee , Hyung-Kyu Yim
发明人： Jung-Hyuk Choi , Soo-Chul Lee , Hyung-Kyu Yim
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L21/8247 , H01L23/528 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L23/528 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7885 , H01L2924/0002
摘要： An electrically erasable programmable semiconductor memory array for high density including a plurality of column lines; a plurality of reference lines perpendicular to the column lines; a plurality of memory strings arranged in two columns at both sides of each column line and in upper and lower rows between the reference lines, each of upper and lower memory strings at one side of each column including a first transistor and a plurality of floating gate transistors, each of upper and lower memory strings at the other side of each column including a second transistor and a plurality of floating gate transistors, drain-source paths of the first or second transistor and the floating gate transistors in each memory string being connected in series, the first and second transistors and the floating gate transistors being arranged in an array of rows and columns, gates of the first and second transistors and the floating gate transistors in the upper memory strings and the first and second transistors and the floating gate transistors in the lower memory strings being respectively connected to first and second select lines, each other upper word lines, third and fourth select lines and each other lower word lines. The drains of the first and second transistors are connected to the column line through a single contact hole; the other ends of the serial connections in the upper memory strings are connected to the reference line adjacent thereto; and means for connecting the other ends of the serial connections in the lower memory strings to the reference line adjacent thereto.
摘要翻译：一种用于高密度的电可擦除可编程半导体存储器阵列，包括多个列线; 垂直于列线的多个参考线; 在列列线的两侧排列成两列的多个存储器串和参考线之间的上下行中的每一列的每一列的每一列包括第一晶体管和多个浮置栅极晶体管，每列包括第二晶体管和多个浮置栅极晶体管的每列的另一侧的每个上和下存储器串，每个存储器串中的第一或第二晶体管的漏极 - 源极路径和浮置栅极晶体管被连接串联的第一和第二晶体管和浮置栅极晶体管布置成行和列的阵列，第一和第二晶体管的栅极和上部存储器串中的浮动栅极晶体管以及第一和第二晶体管以及浮动栅极晶体管在下部存储器串分别连接到第一和第二选择线，彼此之间的上部字线，第三和第四个字母 ect线和彼此较低的字线。第一和第二晶体管的漏极通过单个接触孔连接到列线; 上部存储器串中的串行连接的另一端连接到与其相邻的参考线; 以及用于将下部存储器串中的串行连接的另一端连接到与其相邻的参考线的装置。

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