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1. 发明授权

US4962481A EEPROM device with plurality of memory strings made of floating gate transistors connected in series 失效
标题翻译：具有由串联连接的浮栅晶体管构成的多个存储串的EEPROM器件
公开(公告)号：US4962481A
公开(公告)日：1990-10-09
申请号：US292107
申请日：1988-12-30
申请人： Jung-Hyuk Choi , Soo-Chul Lee , Hyung-Kyu Yim
发明人： Jung-Hyuk Choi , Soo-Chul Lee , Hyung-Kyu Yim
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L21/8247 , H01L23/528 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L23/528 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7885 , H01L2924/0002
摘要： An electrically erasable programmable semiconductor memory array for high density including a plurality of column lines; a plurality of reference lines perpendicular to the column lines; a plurality of memory strings arranged in two columns at both sides of each column line and in upper and lower rows between the reference lines, each of upper and lower memory strings at one side of each column including a first transistor and a plurality of floating gate transistors, each of upper and lower memory strings at the other side of each column including a second transistor and a plurality of floating gate transistors, drain-source paths of the first or second transistor and the floating gate transistors in each memory string being connected in series, the first and second transistors and the floating gate transistors being arranged in an array of rows and columns, gates of the first and second transistors and the floating gate transistors in the upper memory strings and the first and second transistors and the floating gate transistors in the lower memory strings being respectively connected to first and second select lines, each other upper word lines, third and fourth select lines and each other lower word lines. The drains of the first and second transistors are connected to the column line through a single contact hole; the other ends of the serial connections in the upper memory strings are connected to the reference line adjacent thereto; and means for connecting the other ends of the serial connections in the lower memory strings to the reference line adjacent thereto.
摘要翻译：一种用于高密度的电可擦除可编程半导体存储器阵列，包括多个列线; 垂直于列线的多个参考线; 在列列线的两侧排列成两列的多个存储器串和参考线之间的上下行中的每一列的每一列的每一列包括第一晶体管和多个浮置栅极晶体管，每列包括第二晶体管和多个浮置栅极晶体管的每列的另一侧的每个上和下存储器串，每个存储器串中的第一或第二晶体管的漏极 - 源极路径和浮置栅极晶体管被连接串联的第一和第二晶体管和浮置栅极晶体管布置成行和列的阵列，第一和第二晶体管的栅极和上部存储器串中的浮动栅极晶体管以及第一和第二晶体管以及浮动栅极晶体管在下部存储器串分别连接到第一和第二选择线，彼此之间的上部字线，第三和第四个字母 ect线和彼此较低的字线。第一和第二晶体管的漏极通过单个接触孔连接到列线; 上部存储器串中的串行连接的另一端连接到与其相邻的参考线; 以及用于将下部存储器串中的串行连接的另一端连接到与其相邻的参考线的装置。

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