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1. 发明申请

US20050077923A1 Voltage trimming circuit 失效
标题翻译：电压调整电路
公开(公告)号：US20050077923A1
公开(公告)日：2005-04-14
申请号：US10681647
申请日：2003-10-08
申请人： Jung Kim , Jungwon Suh
发明人： Jung Kim , Jungwon Suh
IPC分类号： G05F1/10 , G11C5/14 , G11C29/02 , H03D1/00
CPC分类号： G11C29/021 , G11C5/147 , G11C29/02 , G11C29/028
摘要： Methods and circuits for minimizing or eliminating the effect of trimming circuits in a voltage generating circuit are provided. In general, the effects of channel resistance of switches of the trimming circuit are reduced by utilizing switches in series with the output, rather than in parallel with resistors, as in conventional trimming circuits. Because the switches are not in parallel with the resistors, when the switches are turned on, no channel resistance is added to the effective resistance controlled by the trimming circuit.
摘要翻译：提供了用于最小化或消除电压产生电路中的微调电路的影响的方法和电路。通常，通过利用与输出串联的开关，而不是与传统的微调电路中的电阻并联，减小了微调电路的开关的沟道电阻的影响。由于开关不与电阻并联，因此当开关导通时，由修整电路控制的有效电阻不会增加通道电阻。

2. 发明申请

US20130120050A1 LOW-POWER VOLTAGE REFERENCE CIRCUIT 有权
标题翻译：低功耗电压参考电路
公开(公告)号：US20130120050A1
公开(公告)日：2013-05-16
申请号：US13293850
申请日：2011-11-10
申请人： Wuyang HAO , Jungwon Suh
发明人： Wuyang HAO , Jungwon Suh
IPC分类号： H03K17/14
CPC分类号： G05F3/242
摘要： Methods and apparatus for a providing temperature-compensated reference voltage are provided. In an example, a temperature-compensated voltage reference circuit includes a current mirror portion and a temperature-compensated output portion coupled to the current mirror portion. The temperature-compensated output portion comprises a very low threshold voltage (Vt) transistor coupled in series with a negative temperature coefficient transistor. The output portion can further include a positive temperature coefficient element coupled in series with the very low Vt transistor. The positive temperature coefficient element can be an adjustable resistive element. The output portion can further include an output transistor having a gate coupled to the current mirror portion and coupled between a supply voltage and the positive temperature coefficient element. The very low Vt transistor can be a substantially zero Vt n-channel metal-oxide-semiconductor (NMOS) transistor, and can be coupled in a diode configuration.
摘要翻译：提供了提供温度补偿参考电压的方法和装置。在一个示例中，温度补偿电压参考电路包括耦合到电流镜部分的电流镜部分和温度补偿输出部分。温度补偿输出部分包括与负温度系数晶体管串联耦合的非常低的阈值电压（Vt）晶体管。输出部分还可以包括与极低Vt晶体管串联耦合的正温度系数元件。正温度系数元件可以是可调电阻元件。输出部分还可以包括输出晶体管，其具有耦合到电流镜部分并且耦合在电源电压和正温度系数元件之间的栅极。非常低的Vt晶体管可以是基本为零的Vt n沟道金属氧化物半导体（NMOS）晶体管，并且可以以二极管配置耦合。

3. 发明申请

US20120040712A1 System and Method to Initiate a Housekeeping Operation at a Mobile Device 有权
标题翻译：在移动设备上启动管家操作的系统和方法
公开(公告)号：US20120040712A1
公开(公告)日：2012-02-16
申请号：US12855045
申请日：2010-08-12
申请人： Thomas R. Toms , Hari M. Rao , Seung H. Kang , Jung Pill Kim , Jungwon Suh
发明人： Thomas R. Toms , Hari M. Rao , Seung H. Kang , Jung Pill Kim , Jungwon Suh
IPC分类号： H04W88/02
CPC分类号： G11C16/3418 , G06F1/263 , G06F11/1048
摘要： A system and method to initiate a housekeeping operation at a mobile device is disclosed. In a particular embodiment, a method at a mobile device includes modifying a scheduled housekeeping operation in response to determining that the mobile device is in a charging mode.
摘要翻译：公开了一种在移动设备上启动内务管理操作的系统和方法。在特定实施例中，移动设备处的方法包括响应于确定移动设备处于充电模式来修改排程的内务管理操作。

4. 发明申请

US20120033490A1 Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction 有权
标题翻译：在具有第一磁隧道结和第二磁隧道结的位单元处产生不可逆状态
公开(公告)号：US20120033490A1
公开(公告)日：2012-02-09
申请号：US12849043
申请日：2010-08-03
申请人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
发明人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
IPC分类号： G11C11/14 , G06F17/50 , G11C29/00
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

5. 发明授权

US07545192B2 Clock stop detector 有权
标题翻译：时钟停止检测器
公开(公告)号：US07545192B2
公开(公告)日：2009-06-09
申请号：US11504923
申请日：2006-08-16
申请人： Jungwon Suh
发明人： Jungwon Suh
IPC分类号： H03K17/22 , G11C8/00
CPC分类号： G06F1/3225
摘要： A clock stop detector for a memory comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second switch that closes in response to a second logic level of the clock signal to discharge the capacitor, and a logic circuit that outputs a control signal based on an inverted clock signal and a charge on the capacitor.
摘要翻译：用于存储器的时钟停止检测器包括响应于时钟信号的第一逻辑电平而关闭以对电容器充电的第一开关，响应于时钟信号的第二逻辑电平而闭合以对电容器放电的第二开关，以及逻辑电路，其基于反相时钟信号和电容器上的电荷输出控制信号。

6. 发明申请

US20070140032A1 Sensing Current Recycling Method During Self-Refresh 审中-公开
标题翻译：自刷新期间感应当前回收方法
公开(公告)号：US20070140032A1
公开(公告)日：2007-06-21
申请号：US11677457
申请日：2007-02-21
申请人： Jungwon Suh
发明人： Jungwon Suh
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C7/12 , G11C11/406 , G11C11/4094
摘要： A bit line sensing scheme is provided for a semiconductor memory device that significantly reduces current drain during a self-refresh mode. After bit line sensing of a selected wordline and deactivation of the selected wordline, a capacitor is connected to a source node associated with a bit line sensing amplifier for the selected wordline to charge the capacitor with charge remaining on the bit line. Then, during the next activate-precharge cycle for another selected wordline, the capacitor is coupled to the source node of a bit line sensing amplifier associated with another selected wordline to discharge charge stored by the capacitor to the bit line associated with said other selected wordline. Thus, charge is returned from the bit line to the capacitor. This is where the self-refresh current reduction is achieved.
摘要翻译：为半导体存储器件提供位线检测方案，其在自刷新模式期间显着减少电流消耗。在对所选择的字线进行位线检测和停用所选择的字线之后，将电容器连接到与用于选定字线的位线检测放大器相关联的源节点，以对位线上剩余电荷充电电容器。然后，在下一个激活预充电循环期间，对于另一个选定的字线，电容器耦合到与另一选定字线相关联的位线感测放大器的源节点，以将由电容器存储的电荷放电到与所述另一选定字线相关联的位线。因此，电荷从位线返回到电容器。这是实现自刷新电流降低的地方。

7. 发明授权

US07146456B2 Memory device with a flexible reduced density option 失效
标题翻译：具有灵活的减少密度选项的存储设备
公开(公告)号：US07146456B2
公开(公告)日：2006-12-05
申请号：US10673626
申请日：2003-09-29
申请人： Jungwon Suh
发明人： Jungwon Suh
IPC分类号： G06F12/00
CPC分类号： G11C29/883 , G11C7/1045 , G11C11/401 , G11C11/4076 , G11C11/4097 , G11C29/88
摘要： A dynamic random access memory device is capable of converting from a full density memory device to a reduced density memory device. The reduced density memory device compensates for cell failures in a plurality of cell blocks, regardless of the location of the cell failures. The memory device includes a row address mapping fuse for selectively determining row address combinations capable of storing data bits. A row address mapping logic is coupled to the row address mapping fuse and is capable of routing data bits to the address combinations capable of storing data bits.
摘要翻译：动态随机存取存储器件能够从全密度存储器件转换为精密密度存储器件。减小密度存储器件补偿多个单元块中的单元故障，而不管单元故障的位置。存储器件包括用于选择性地确定能够存储数据位的行地址组合的行地址映射熔丝。行地址映射逻辑耦合到行地址映射熔丝，并且能够将数据位路由到能够存储数据位的地址组合。

8. 发明申请

US20060242448A1 Circuit including a deskew circuit 有权
标题翻译：电路包括一个歪斜电路
公开(公告)号：US20060242448A1
公开(公告)日：2006-10-26
申请号：US11111140
申请日：2005-04-21
申请人： Alessandro Minzoni , Jungwon Suh
发明人： Alessandro Minzoni , Jungwon Suh
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H03K5/06
摘要： A circuit including a deskew circuit. The deskew circuit is configured to receive a first signal having a first edge delayed from a second edge of a second signal by a first delay and a third edge delayed from a fourth edge of the second signal by a second delay. The deskew circuit is configured to provide a third signal having a first deskewed edge delayed from the first edge by a third delay and a second deskewed edge delayed from the third edge by a fourth delay. The difference between the fourth delay and the third delay is substantially equal to the difference between the first delay and the second delay.
摘要翻译：包括歪斜电路的电路。歪斜电路被配置为接收具有从第二信号的第二边缘延迟的第一边缘第一延迟的第一信号和从第二信号的第四边缘延迟第二延迟的第三边沿。该去歪斜电路被配置为提供具有从第一边缘延迟了第三延迟的第一偏斜偏移边缘和从第三边缘延迟第四延迟的第二偏斜边缘的第三信号。第四延迟和第三延迟之间的差异基本上等于第一延迟和第二延迟之间的差。

9. 发明授权

US06861872B2 Voltage down converter for low voltage operation 有权
标题翻译：降压转换器用于低电压工作
公开(公告)号：US06861872B2
公开(公告)日：2005-03-01
申请号：US10358581
申请日：2003-02-05
申请人： Jungwon Suh
发明人： Jungwon Suh
IPC分类号： H03K19/0185 , H04L25/02 , H03K19/0175
CPC分类号： H03K19/018578
摘要： A voltage down converter for a semiconductor memory device to convert an external voltage to a lower value internal voltage for the device, has a voltage generator that produces a reference voltage corresponding to the value of the internal voltage, a comparator having opposite polarity inputs for producing an amplified output control signal, and a pull-up device operating from the external voltage that receives the control signal from the comparator to produce the internal voltage as an input. A dual source follower is located between the reference voltage generator and comparator and has two sections having cross-coupled inputs which respectively receive the internal reference voltage and the internal voltage to produce output voltages moving in opposite directions, each of which is applied to one input of the comparator, thereby translating the difference between Vintref and Vint to a level in a range that can be better amplified by the comparator.
摘要翻译：用于将外部电压转换为器件的较低值内部电压的半导体存储器件的降压转换器具有产生与内部电压值相对应的参考电压的电压发生器，具有相反极性输入的比较器，用于产生放大的输出控制信号和从外部电压工作的上拉装置，其接收来自比较器的控制信号以产生内部电压作为输入。双源极跟随器位于参考电压发生器和比较器之间，并且具有两个部分，其交叉耦合输入分别接收内部参考电压和内部电压，以产生沿相反方向移动的输出电压，每个输入电压施加到一个输入端的比较器，从而将Vintref和Vint之间的差异转换为可以被比较器更好地放大的范围内的电平。

10. 发明授权

US08493134B2 Method and apparatus to provide a clock signal to a charge pump 失效
标题翻译：向电荷泵提供时钟信号的方法和装置
公开(公告)号：US08493134B2
公开(公告)日：2013-07-23
申请号：US12729281
申请日：2010-03-23
申请人： Wuyang Hao , Jung Pill Kim , Jungwon Suh
发明人： Wuyang Hao , Jung Pill Kim , Jungwon Suh
IPC分类号： G05F1/10
CPC分类号： G06F1/06 , H02M3/07 , H02M3/073 , H02M2003/077
摘要： A method and apparatus for providing a clock signal to a charge pump is disclosed. In a particular embodiment, the method includes providing a first clock signal to a first charge pump unit of a charge pump. The method further includes providing a second clock signal to a second charge pump unit of the charge pump. A low-to-high transition of the first clock signal occurs substantially concurrently with a high-to-low transition of the second clock signal. Only one clock signal may be at a logic high voltage level at any given time.
摘要翻译：公开了一种用于向电荷泵提供时钟信号的方法和装置。在特定实施例中，该方法包括向电荷泵的第一电荷泵单元提供第一时钟信号。该方法还包括向电荷泵的第二电荷泵单元提供第二时钟信号。第一时钟信号的从低到高的跃迁与第二时钟信号的高到低的跃迁基本同时发生。在任何给定时间，只有一个时钟信号可能处于逻辑高电压电平。

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