专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120033490A1 Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction 有权
标题翻译：在具有第一磁隧道结和第二磁隧道结的位单元处产生不可逆状态
公开(公告)号：US20120033490A1
公开(公告)日：2012-02-09
申请号：US12849043
申请日：2010-08-03
申请人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
发明人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
IPC分类号： G11C11/14 , G06F17/50 , G11C29/00
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

2. 发明授权

US08547736B2 Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction 有权
标题翻译：在具有第一磁性隧道结和第二磁性隧道结的位单元处产生不可逆状态
公开(公告)号：US08547736B2
公开(公告)日：2013-10-01
申请号：US12849043
申请日：2010-08-03
申请人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
发明人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

3. 发明授权

US08639943B2 Methods and systems for checking run-time integrity of secure code cross-reference to related applications 有权
标题翻译：用于检查安全代码的运行时完整性的方法和系统交叉引用到相关应用程序
公开(公告)号：US08639943B2
公开(公告)日：2014-01-28
申请号：US12485089
申请日：2009-06-16
申请人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
发明人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译：公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。指示许可的TLB许可条目是无效的，导致访问页面的按需认证。认证后，TLB中的许可条目被更新以反映该页面已被认证。作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

4. 发明申请

US20110241741A1 SYSTEM AND METHOD TO CONTROL A POWER ON RESET SIGNAL 失效
标题翻译：控制上电复位信号的系统和方法
公开(公告)号：US20110241741A1
公开(公告)日：2011-10-06
申请号：US12752027
申请日：2010-03-31
申请人： Steven M. Millendorf , Michael K. Batenburg , Sarath Chandra Kasarla
发明人： Steven M. Millendorf , Michael K. Batenburg , Sarath Chandra Kasarla
IPC分类号： H03L7/00 , G06F17/30 , G06F19/00
CPC分类号： H03K17/22 , G06F1/24 , H03K3/84
摘要： A system and method to control a power on reset signal is disclosed. In a particular embodiment, a power on reset circuit includes a first linear feedback shift register and a second linear feedback shift register. The first linear feedback shift register is configured to operate at least partially in parallel with the second linear feedback shift register.
摘要翻译：公开了一种控制上电复位信号的系统和方法。在特定实施例中，上电复位电路包括第一线性反馈移位寄存器和第二线性反馈移位寄存器。第一线性反馈移位寄存器被配置为至少部分地与第二线性反馈移位寄存器并行操作。

5. 发明申请

US20090313695A1 Methods and Systems for Checking Run-Time Integrity of Secure Code Cross-Reference to Related Applications 有权
标题翻译：用于检查安全代码交叉引用到相关应用程序的运行时完整性的方法和系统
公开(公告)号：US20090313695A1
公开(公告)日：2009-12-17
申请号：US12485089
申请日：2009-06-16
申请人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
发明人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
IPC分类号： G06F12/14
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译：公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。指示许可的TLB许可条目是无效的，导致访问页面的按需认证。认证后，TLB中的许可条目被更新以反映该页面已被认证。作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

6. 发明授权

US08560987B2 Test functionality integrity verification for integrated circuit design 失效
标题翻译：集成电路设计的测试功能完整性验证
公开(公告)号：US08560987B2
公开(公告)日：2013-10-15
申请号：US13484222
申请日：2012-05-30
申请人： Steven M. Millendorf
发明人： Steven M. Millendorf
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/14
摘要： Systems and methods are provided for verifying the integrity of test functionality for an integrated circuit design. This may be achieved, for example, by analyzing the integrated circuit design to identify a driver element that outputs a security signal for controlling the test functionality, analyzing the integrated circuit design to identify an input stage of one or more elements that feed the driver element, monitoring the security signal over a range of values for the input stage, and determining that an error exists in the test functionality if a change in the security signal is detected during the monitoring.
摘要翻译：提供了系统和方法来验证集成电路设计的测试功能的完整性。这可以通过例如分析集成电路设计来识别输出用于控制测试功能的安全信号的驱动器元件来实现，分析集成电路设计以识别馈送驱动器元件的一个或多个元件的输入级在输入级的一定范围内监视安全信号，并且如果在监视期间检测到安全信号的变化，则确定测试功能中存在错误。

7. 发明授权

US08493109B2 System and method to control a power on reset signal 失效
标题翻译：控制上电复位信号的系统和方法
公开(公告)号：US08493109B2
公开(公告)日：2013-07-23
申请号：US12752027
申请日：2010-03-31
申请人： Steven M. Millendorf , Michael K. Batenburg , Sarath Chandra Kasarla
发明人： Steven M. Millendorf , Michael K. Batenburg , Sarath Chandra Kasarla
IPC分类号： H03L7/00
CPC分类号： H03K17/22 , G06F1/24 , H03K3/84
摘要： A system and method to control a power on reset signal is disclosed. In a particular embodiment, a power on reset circuit includes a first linear feedback shift register and a second linear feedback shift register. The first linear feedback shift register is configured to operate at least partially in parallel with the second linear feedback shift register.
摘要翻译：公开了一种控制上电复位信号的系统和方法。在特定实施例中，上电复位电路包括第一线性反馈移位寄存器和第二线性反馈移位寄存器。第一线性反馈移位寄存器被配置为至少部分地与第二线性反馈移位寄存器并行操作。

8. 发明申请

US20130074023A1 Test Functionality Integrity Verification for Integrated Circuit Design 失效
标题翻译：集成电路设计的测试功能完整性验证
公开(公告)号：US20130074023A1
公开(公告)日：2013-03-21
申请号：US13484222
申请日：2012-05-30
申请人： Steven M. Millendorf
发明人： Steven M. Millendorf
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/14
摘要： Systems and methods are provided for verifying the integrity of test functionality for an integrated circuit design. This may be achieved, for example, by analyzing the integrated circuit design to identify a driver element that outputs a security signal for controlling the test functionality, analyzing the integrated circuit design to identify an input stage of one or more elements that feed the driver element, monitoring the security signal over a range of values for the input stage, and determining that an error exists in the test functionality if a change in the security signal is detected during the monitoring.
摘要翻译：提供了系统和方法来验证集成电路设计的测试功能的完整性。这可以通过例如分析集成电路设计来识别输出用于控制测试功能的安全信号的驱动器元件来实现，分析集成电路设计以识别馈送驱动器元件的一个或多个元件的输入级在输入级的一定范围内监视安全信号，并且如果在监视期间检测到安全信号的变化，则确定测试功能中存在错误。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式