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1. 发明授权

US07591714B2 Wafer grinding and tape attaching apparatus and method 失效
标题翻译：晶圆研磨和贴附装置及方法
公开(公告)号：US07591714B2
公开(公告)日：2009-09-22
申请号：US11397883
申请日：2006-04-05
申请人： Jun-Young Ko , Dae-Sang Chan , Sang-Jun Kim
发明人： Jun-Young Ko , Dae-Sang Chan , Sang-Jun Kim
IPC分类号： B25B7/00
CPC分类号： B24B7/228 , B24B37/345
摘要： A wafer grinding and tape attaching apparatus and method, the method includes providing a wafer to a chuck table, grinding a back side of the wafer, providing a wafer ring having dicing tape and attaching the dicing tape to the back side of the ground wafer.
摘要翻译：一种晶片研磨和胶带附着装置及方法，该方法包括将晶片提供到卡盘台，研磨晶片的背面，提供具有切割带的晶片环，并将切割带附接到研磨晶片的背面。

2. 发明申请

US20070099550A1 Wafer grinding and tape attaching apparatus and method 失效
标题翻译：晶圆研磨和贴附装置及方法
公开(公告)号：US20070099550A1
公开(公告)日：2007-05-03
申请号：US11397883
申请日：2006-04-05
申请人： Jun-Young Ko , Dae-Sang Chan , Sang-Jun Kim
发明人： Jun-Young Ko , Dae-Sang Chan , Sang-Jun Kim
IPC分类号： B24B7/30 , B24B1/00 , B24B29/00
CPC分类号： B24B7/228 , B24B37/345
摘要： A wafer grinding and tape attaching apparatus and method, the method includes providing a wafer to a chuck table, grinding a back side of the wafer, providing a wafer ring having dicing tape and attaching the dicing tape to the back side of the ground wafer.
摘要翻译：一种晶片研磨和胶带附着装置及方法，该方法包括将晶片提供到卡盘台，研磨晶片的背面，提供具有切割带的晶片环，并将切割带附接到研磨晶片的背面。

3. 发明申请

US20140232373A1 METHOD AND DEVICE FOR DETECTING ZERO PHASE COMPONENT 有权
标题翻译：用于检测零相分量的方法和装置
公开(公告)号：US20140232373A1
公开(公告)日：2014-08-21
申请号：US14342153
申请日：2011-09-30
申请人： Yong Up Park , Won Suck Choi , Byung Sung Lee , Sun Kyu Choi , Kil Sin Kim , Seok Gon Kim , Sang-Jun Kim
发明人： Yong Up Park , Won Suck Choi , Byung Sung Lee , Sun Kyu Choi , Kil Sin Kim , Seok Gon Kim , Sang-Jun Kim
IPC分类号： G01R25/00
CPC分类号： G01R25/00 , G01R29/16
摘要： There are provided a method and device for detecting a zero phase component. The device for detecting a zero phase component includes a meter chip of a sequential sampling method, a data acquiring unit configured to acquire sequential data on a plurality of phases from the meter chip, and a zero phase current value calculating unit configured to calculate an instantaneous current value for fault detection by summing instantaneous current values for each phase from the acquired sequential data, and calculate a zero phase current value using the calculated instantaneous current value for fault detection.
摘要翻译：提供了一种用于检测零相分量的方法和装置。用于检测零相位分量的装置包括顺序采样方法的仪表芯片，数据获取单元，被配置为从仪表芯片获取关于多个相位的顺序数据;以及零相电流值计算单元，被配置为计算瞬时通过从所获取的顺序数据求和每相的瞬时电流值求和故障检测的当前值，并使用所计算的用于故障检测的瞬时电流值来计算零相电流值。

4. 发明授权

US09671440B2 Method and device for detecting zero phase component 有权
公开(公告)号：US09671440B2
公开(公告)日：2017-06-06
申请号：US14342153
申请日：2011-09-30
申请人： Yong Up Park , Won Suck Choi , Byung Sung Lee , Sun Kyu Choi , Kil Sin Kim , Seok Gon Kim , Sang-Jun Kim
发明人： Yong Up Park , Won Suck Choi , Byung Sung Lee , Sun Kyu Choi , Kil Sin Kim , Seok Gon Kim , Sang-Jun Kim
IPC分类号： G01R25/00 , G01R29/16
CPC分类号： G01R25/00 , G01R29/16
摘要： There are provided a method and device for detecting a zero phase component. The device for detecting a zero phase component includes a meter chip of a sequential sampling method, a data acquiring unit configured to acquire sequential data on a plurality of phases from the meter chip, and a zero phase current value calculating unit configured to calculate an instantaneous current value for fault detection by summing instantaneous current values for each phase from the acquired sequential data, and calculate a zero phase current value using the calculated instantaneous current value for fault detection.

5. 发明授权

US09347977B2 Connection error detecting apparatus and method which detect a connection error in a smart meter 有权
标题翻译：用于检测智能电表中的连接错误的连接错误检测装置和方法
公开(公告)号：US09347977B2
公开(公告)日：2016-05-24
申请号：US14239130
申请日：2011-08-17
申请人： Sang-Jun Kim , Tae-Hyo Kim , Woo-Yong Kim , Sang-Suh Park , Sung-Min Kim
发明人： Sang-Jun Kim , Tae-Hyo Kim , Woo-Yong Kim , Sang-Suh Park , Sung-Min Kim
IPC分类号： G08C19/16 , G01R22/06 , G01R31/04 , G01D4/00 , G01R22/10
CPC分类号： G01R22/06 , G01D4/004 , G01R22/10 , G01R31/041 , Y02B90/242 , Y04S20/322
摘要： Provided are a connection error detecting apparatus and method. The connection error detecting apparatus, which detects connection errors for each rating of a smart meter, comprises: a parameter calculating unit for calculating connection error detecting parameters including an actual three-phase voltage value, an actual three-phase current value, an effective amount of three-phase power, and an ineffective amount of three-phase power; and a connection error determining unit for setting connection error criteria for detecting connection errors for each rating of the smart meter, and detecting the connection errors for each rating by determining whether or not any one of the connection error detecting parameters satisfies the connection error criteria.
摘要翻译：提供了连接错误检测装置和方法。检测智能电表的每个额定值的连接错误的连接错误检测装置包括：参数计算单元，用于计算包括实际三相电压值，实际三相电流值，实际三相电流值，有效量的三相电源，三相电源无效; 以及连接错误确定单元，用于设置用于检测智能电表的每个等级的连接错误的连接错误标准，以及通过确定连接错误检测参数中的任何一个是否满足连接错误标准来检测每个等级的连接错误。

6. 发明授权

US07061125B2 Semiconductor package with pattern leads and method for manufacturing the same 失效
标题翻译：带图案引线的半导体封装及其制造方法
公开(公告)号：US07061125B2
公开(公告)日：2006-06-13
申请号：US10667474
申请日：2003-09-23
申请人： Sung-Dae Cho , Sang-Jun Kim , Joo-Hyung Lee
发明人： Sung-Dae Cho , Sang-Jun Kim , Joo-Hyung Lee
IPC分类号： H01L23/29
CPC分类号： H01L24/82 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/25 , H01L2224/24011 , H01L2224/24051 , H01L2224/24226 , H01L2224/24998 , H01L2224/2512 , H01L2224/32225 , H01L2224/73267 , H01L2224/76152 , H01L2224/82007 , H01L2224/82181 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/00
摘要： A semiconductor package utilizing insulating peripheral sealing portions and pattern leads and methods for manufacturing such semiconductor packages are provided. The semiconductor package includes a substrate on which a semiconductor chip is mounted. The substrate includes a plurality of substrate pads and the semiconductor chip includes a plurality of chip pads on an active surface. The semiconductor chip is surrounded by one or more peripheral sealing layers and conductive lead patterns are formed across the peripheral sealing layer(s) to connect the chip pads to corresponding substrate pads. The chip and lead patterns may be encapsulated and the substrate may also be provided with external connection structures such as solder balls to complete the package.
摘要翻译：提供利用绝缘外围密封部分和图案引线的半导体封装以及用于制造这种半导体封装件的方法。半导体封装包括其上安装有半导体芯片的基板。衬底包括多个衬底焊盘，并且半导体芯片在有源表面上包括多个芯片焊盘。半导体芯片由一个或多个外围密封层围绕，并且跨越周边密封层形成导电引线图案，以将芯片焊盘连接到相应的衬底焊盘。可以封装芯片和引线图案，并且衬底也可以设置有外部连接结构，例如焊球以完成封装。

7. 发明申请

US20060082786A1 Apparatus and method for measurement of film thickness using improved fast fourier transformation 失效
标题翻译：使用改进的快速傅里叶变换测量膜厚度的装置和方法
公开(公告)号：US20060082786A1
公开(公告)日：2006-04-20
申请号：US10541876
申请日：2003-06-18
申请人： Sang-Youl Kim , Sang-Jun Kim
发明人： Sang-Youl Kim , Sang-Jun Kim
IPC分类号： G01B11/02
CPC分类号： G01B11/0625
摘要： The present invention relates to an apparatus and method for a measurement of a film thickness using an improved fast Fourier transformation. The apparatus includes a light source, a light receiving unit for converging a light from the light source, a detection unit for splitting a reflection light reflected by the surface of the sample and inputted into the optical fabric through the lens, and outputted to the other side of the optical fabric based on a light intensity of each wavelength and providing a certain amount of wavelength, a conversion unit for converting a wavelength based spectrum data detected by the detection unit into an analog signal and then converting into a digital signal through a converter, a computation unit for computing the number of vibrations based on a high speed Fourier transformation, and an analyzing unit for measuring a film thickness.
摘要翻译：本发明涉及使用改进的快速傅里叶变换来测量膜厚度的装置和方法。该装置包括光源，用于会聚来自光源的光的光接收单元，用于将由样品的表面反射的反射光分离并通过透镜输入到光学织物中的检测单元，并输出到另一个基于每个波长的光强度并提供一定量的波长的转换单元，用于将由检测单元检测到的基于波长的频谱数据转换为模拟信号，然后通过转换器转换成数字信号的转换单元，用于计算基于高速傅里叶变换的振动次数的计算单元和用于测量膜厚度的分析单元。

8. 发明申请

US20140197966A1 CONNECTION ERROR DETECTING APPARATUS AND METHOD WHICH DETECT A CONNECTION ERROR IN A SMART METER 有权
标题翻译：连接错误检测装置和在智能计量器中检测到连接错误的方法
公开(公告)号：US20140197966A1
公开(公告)日：2014-07-17
申请号：US14239130
申请日：2011-08-17
申请人： Sang-Jun Kim , Tae-Hyo Kim , Woo-Yong Kim , Sang-Suh Park , Sung-Min Kim
发明人： Sang-Jun Kim , Tae-Hyo Kim , Woo-Yong Kim , Sang-Suh Park , Sung-Min Kim
IPC分类号： G01R22/06 , G01R31/04
CPC分类号： G01R22/06 , G01D4/004 , G01R22/10 , G01R31/041 , Y02B90/242 , Y04S20/322
摘要： Provided are a connection error detecting apparatus and method. The connection error detecting apparatus, which detects connection errors for each rating of a smart meter, comprises: a parameter calculating unit for calculating connection error detecting parameters including an actual three-phase voltage value, an actual three-phase current value, an effective amount of three-phase power, and an ineffective amount of three-phase power; and a connection error determining unit for setting connection error criteria for detecting connection errors for each rating of the smart meter, and detecting the connection errors for each rating by determining whether or not any one of the connection error detecting parameters satisfies the connection error criteria.
摘要翻译：提供了连接错误检测装置和方法。检测智能电表的每个等级的连接错误的连接错误检测装置包括：参数计算单元，用于计算包括实际三相电压值，实际三相电流值，实际三相电流值，有效量的三相电源，三相电源无效; 以及连接错误确定单元，用于设置用于检测智能电表的每个等级的连接错误的连接错误标准，以及通过确定连接错误检测参数中的任何一个是否满足连接错误标准来检测每个等级的连接错误。

9. 发明申请

US20110026452A1 Apparatus and method of processing rescue request signal 有权
标题翻译：处理救援请求信号的装置及方法
公开(公告)号：US20110026452A1
公开(公告)日：2011-02-03
申请号：US12588943
申请日：2009-11-03
申请人： Yong-Hoon Kang , Sang-Jun Kim , Pil--Kyu Jin
发明人： Yong-Hoon Kang , Sang-Jun Kim , Pil--Kyu Jin
IPC分类号： H04B7/14 , H04B17/02 , H04W24/00
CPC分类号： H04W4/22 , H04B7/155 , H04W4/90 , H04W64/00 , H04W76/50
摘要： Provided is a rescue request signal processing device connected with a repeater and including a signal detector configured to detect identification information of a wireless communication terminal from an uplink signal outputted from the wireless communication terminal; a signal strength information generator configured to generate strength information of the uplink signal of the wireless communication terminal when the detected identification information of the wireless communication terminal is identical with identification information of a wireless communication terminal included in a request signal for location information transmitted from a location information requesting device; and a transmitter configured to transmit the strength information of the uplink signal and at least one of location information and identification information of the repeater to a location information server.
摘要翻译：提供了一种与中继器连接的救援请求信号处理装置，包括：信号检测器，被配置为从无线通信终端输出的上行链路信号检测无线通信终端的识别信息; 信号强度信息生成器，被配置为当所检测的无线通信终端的识别信息与从包含在从无线通信终端发送的位置信息的请求信号中包括的无线通信终端的识别信息相同时，生成无线通信终端的上行链路信号的强度信息位置信息请求装置; 以及发射机，被配置为将上行链路信号的强度信息和中继器的位置信息和识别信息中的至少一个发送到位置信息服务器。

10. 发明申请

US20070052094A1 Semiconductor wafer level chip package and method of manufacturing the same 审中-公开
标题翻译：半导体晶圆级芯片封装及其制造方法
公开(公告)号：US20070052094A1
公开(公告)日：2007-03-08
申请号：US11431084
申请日：2006-05-10
申请人： Goon-Woo Kim , Man-Hee Han , Jae-Hong Kim , Heui-Seog Kim , Sang-Jun Kim , Wha-Su Sin
发明人： Goon-Woo Kim , Man-Hee Han , Jae-Hong Kim , Heui-Seog Kim , Sang-Jun Kim , Wha-Su Sin
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/481 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/0508 , H01L2224/051 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05571 , H01L2224/056 , H01L2224/13024 , H01L2224/16 , H01L2224/274 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/3011 , H01L2924/00014
摘要： A semiconductor chip package may include one or more conductive patterns provided on a front surface of a wafer. An encapsulation layer may cover at least the front surface of the wafer. Chip plugs may be electrically connected to the conductive patterns, and may be embedded in a rear surface of the wafer. External connection terminals may be electrically connected to the chip plugs, and may be provided on the rear surface of the wafer.
摘要翻译：半导体芯片封装可以包括设置在晶片的前表面上的一个或多个导电图案。封装层可以至少覆盖晶片的前表面。芯片插头可以电连接到导电图案，并且可以嵌入在晶片的后表面中。外部连接端子可以电连接到芯片插头，并且可以设置在晶片的后表面上。

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