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1. 发明申请

US20070052094A1 Semiconductor wafer level chip package and method of manufacturing the same 审中-公开
标题翻译：半导体晶圆级芯片封装及其制造方法
公开(公告)号：US20070052094A1
公开(公告)日：2007-03-08
申请号：US11431084
申请日：2006-05-10
申请人： Goon-Woo Kim , Man-Hee Han , Jae-Hong Kim , Heui-Seog Kim , Sang-Jun Kim , Wha-Su Sin
发明人： Goon-Woo Kim , Man-Hee Han , Jae-Hong Kim , Heui-Seog Kim , Sang-Jun Kim , Wha-Su Sin
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/481 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/0508 , H01L2224/051 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05571 , H01L2224/056 , H01L2224/13024 , H01L2224/16 , H01L2224/274 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/3011 , H01L2924/00014
摘要： A semiconductor chip package may include one or more conductive patterns provided on a front surface of a wafer. An encapsulation layer may cover at least the front surface of the wafer. Chip plugs may be electrically connected to the conductive patterns, and may be embedded in a rear surface of the wafer. External connection terminals may be electrically connected to the chip plugs, and may be provided on the rear surface of the wafer.
摘要翻译：半导体芯片封装可以包括设置在晶片的前表面上的一个或多个导电图案。封装层可以至少覆盖晶片的前表面。芯片插头可以电连接到导电图案，并且可以嵌入在晶片的后表面中。外部连接端子可以电连接到芯片插头，并且可以设置在晶片的后表面上。

2. 发明申请

US20060003491A1 Apparatus for ejecting relatively thin IC chip from semiconductor wafer 审中-公开
标题翻译：用于从半导体晶片排出相对薄的IC芯片的装置
公开(公告)号：US20060003491A1
公开(公告)日：2006-01-05
申请号：US11153750
申请日：2005-06-14
申请人： Goon-Woo Kim , Heui-Seog Kim , Jong-Keun Jeon , Wha-Su Sin , Jong-Ung Lee
发明人： Goon-Woo Kim , Heui-Seog Kim , Jong-Keun Jeon , Wha-Su Sin , Jong-Ung Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/67132
摘要： An apparatus and method for ejecting a thin IC chip from a UV-sensitive tape attached to a bottom face of a semiconductor wafer, includes a vacuum holder that partly supports the UV-sensitive tape by applying vacuum force. The apparatus further includes an ejecting block inserted in the vacuum holder and configured to move vertically relative to the vacuum holder, and a plurality of ejecting pins inserted in the ejecting block and configured to move vertically and elastically. The ejecting pins move upward from the ejecting block driven by a pin-driving plate, detaching the IC chip from the UV-sensitive tape. Then the ejecting block moves upward from the vacuum holder driven by a block-driving shaft, applying a pressure to the bottom face of the IC chip.
摘要翻译：从安装在半导体晶片底面的紫外线敏感胶带排出薄IC芯片的装置和方法包括通过施加真空力部分地支撑UV敏感胶带的真空支架。所述装置还包括插入所述真空保持器中并被配置为相对于所述真空保持件垂直移动的排出块，以及插入所述排出块中并被构造成垂直和弹性移动的多个排出销。排出销从由销驱动板驱动的排出块向上移动，将IC芯片从紫外线敏感胶带分离。然后，排出块从由块驱动轴驱动的真空保持器向上移动，向IC芯片的底面施加压力。

3. 发明授权

US07452753B2 Method of processing a semiconductor wafer for manufacture of semiconductor device 失效
标题翻译：用于制造半导体器件的半导体晶片的处理方法
公开(公告)号：US07452753B2
公开(公告)日：2008-11-18
申请号：US11172689
申请日：2005-06-30
申请人： Dae-Sang Chun , Jae-Hong Kim , Heui-Seog Kim , Jong-Keun Jeon , Wha-Su Sin
发明人： Dae-Sang Chun , Jae-Hong Kim , Heui-Seog Kim , Jong-Keun Jeon , Wha-Su Sin
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L21/6835 , H01L2221/6834 , H01L2221/68354 , H01L2221/68368
摘要： A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface. The method includes forming grooves of a predetermined depth on the second surface on which circuit patterns are formed, attaching a first surface of a protective tape to the second surface on which the grooves are formed, attaching a carrier tape to a second surface of the protective tape opposite to the first surface of the protective tape so that the first surface of the semiconductor wafer can be oriented upward, removing the first surface of the semiconductor wafer by a predetermined thickness and dividing the semiconductor wafer into chips by the grooves, and supplying each chip to a die bonder in the state where the first surface of the of the chip is oriented upward. Only one kind of die bonder is needed. A UV-type tape is not required.
摘要翻译：一种处理具有与第一表面相对的第一表面和第二表面的半导体晶片的方法。该方法包括在其上形成有电路图案的第二表面上形成预定深度的凹槽，将保护带的第一表面附接到其上形成有凹槽的第二表面，将载带附着到保护层的第二表面上带，使得半导体晶片的第一表面可以向上取向，将半导体晶片的第一表面除去预定的厚度，并通过凹槽将半导体晶片分成芯片，并将每个在芯片的第一表面朝向上方的状态下的芯片接合器。只需要一种管芯焊接机。不需要UV型胶带。

4. 发明授权

US07420814B2 Package stack and manufacturing method thereof 有权
标题翻译：封装堆栈及其制造方法
公开(公告)号：US07420814B2
公开(公告)日：2008-09-02
申请号：US11100525
申请日：2005-04-07
申请人： Jae-Hong Kim , Heui-Seog Kim , Wha-Su Sin , Jong-Keun Jeon
发明人： Jae-Hong Kim , Heui-Seog Kim , Wha-Su Sin , Jong-Keun Jeon
IPC分类号： H05K1/14
CPC分类号： H01L25/105 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/3511
摘要： A package stack may include a first package and a second package. The first package may have an IC chip with an active surface and a back surface. The active surface may be connected to a first major surface of a first circuit substrate. The second package may include a second IC chip with an active surface and a back surface. The back surface of the second IC chip may be attached to a first major surface of a second circuit substrate and the active surface of the second IC chip may be electrically connected to the first major surface of the second circuit substrate. The first package may be stacked on the second package so that the active surface of the second package may be electrically connected to a second major surface of the first circuit substrate of the first package. A method may involve providing a first package having a first IC chip and a first circuit substrate and providing a second package having a second IC chip and a second circuit substrate. The first and the second packages may be stacked so that the active surface of the second IC may face and be electrically connected to a major surface of the first circuit substrate.
摘要翻译：包装堆叠可以包括第一包装和第二包装。第一封装可以具有带有活性表面和背面的IC芯片。有源表面可以连接到第一电路基板的第一主表面。第二封装可以包括具有有源表面和后表面的第二IC芯片。第二IC芯片的背面可以附接到第二电路基板的第一主表面，并且第二IC芯片的有源表面可以电连接到第二电路基板的第一主表面。第一封装可以堆叠在第二封装上，使得第二封装的有源表面可以电连接到第一封装的第一电路基板的第二主表面。一种方法可以包括提供具有第一IC芯片和第一电路基板的第一封装，并提供具有第二IC芯片和第二电路基板的第二封装。可以堆叠第一和第二封装，使得第二IC的有源表面可以面对并且电连接到第一电路基板的主表面。

5. 发明申请

US20060057833A1 Method of forming solder ball, and fabricating method and structure of semiconductor package using the same 有权
标题翻译：形成焊球的方法，以及使用其制造半导体封装的方法和结构
公开(公告)号：US20060057833A1
公开(公告)日：2006-03-16
申请号：US11070212
申请日：2005-03-03
申请人： Jae-Hong Kim , Heui-Seog Kim , Wha-Su Sin , Jong-Keun Jeon
发明人： Jae-Hong Kim , Heui-Seog Kim , Wha-Su Sin , Jong-Keun Jeon
IPC分类号： H01L21/44
CPC分类号： H01L23/3128 , H01L21/4867 , H01L21/563 , H01L23/3114 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/1134 , H01L2224/131 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2225/0651 , H01L2225/06568 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K3/3484 , H05K3/4015 , H05K2201/0367 , H05K2201/10734 , H05K2203/043 , H05K2203/049 , H01L2224/13099 , H01L2924/00012 , H01L2924/00 , H01L2924/20752 , H01L2924/20755 , H01L2924/2075 , H01L2924/20754 , H01L2224/0401
摘要： A method of forming solder balls may involve forming bumps through wire boding on land patterns of a circuit substrate. Solder cream may be applied to the bumps through screen printing. The solder cream may be melted via reflow to form solder balls in which the bumps are embedded.
摘要翻译：形成焊球的方法可以包括通过在电路基板的焊盘图案上的导线形成来形成凸块。焊膏可以通过丝网印刷施加到凸块上。焊膏可以通过回流熔化以形成其中嵌入凸块的焊球。

6. 发明授权

US07427558B2 Method of forming solder ball, and fabricating method and structure of semiconductor package using the same 有权
标题翻译：形成焊球的方法，以及使用其制造半导体封装的方法和结构
公开(公告)号：US07427558B2
公开(公告)日：2008-09-23
申请号：US11070212
申请日：2005-03-03
申请人： Jae-Hong Kim , Heui-Seog Kim , Wha-Su Sin , Jong-Keun Jeon
发明人： Jae-Hong Kim , Heui-Seog Kim , Wha-Su Sin , Jong-Keun Jeon
IPC分类号： H01L21/44
CPC分类号： H01L23/3128 , H01L21/4867 , H01L21/563 , H01L23/3114 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/1134 , H01L2224/131 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2225/0651 , H01L2225/06568 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K3/3484 , H05K3/4015 , H05K2201/0367 , H05K2201/10734 , H05K2203/043 , H05K2203/049 , H01L2224/13099 , H01L2924/00012 , H01L2924/00 , H01L2924/20752 , H01L2924/20755 , H01L2924/2075 , H01L2924/20754 , H01L2224/0401
摘要： A method of forming solder balls may involve forming bumps through wire boding on land patterns of a circuit substrate. Solder cream may be applied to the bumps through screen printing. The solder cream may be melted via reflow to form solder balls in which the bumps are embedded.
摘要翻译：形成焊球的方法可以包括通过在电路基板的焊盘图案上的导线形成来形成凸块。焊膏可以通过丝网印刷施加到凸块上。焊膏可以通过回流熔化以形成其中嵌入凸块的焊球。

7. 发明申请

US20060076665A1 Package stack and manufacturing method thereof 有权
标题翻译：封装堆栈及其制造方法
公开(公告)号：US20060076665A1
公开(公告)日：2006-04-13
申请号：US11100525
申请日：2005-04-07
申请人： Jae-Hong Kim , Heui-Seog Kim , Wha-Su Sin , Jong-Keun Jeon
发明人： Jae-Hong Kim , Heui-Seog Kim , Wha-Su Sin , Jong-Keun Jeon
IPC分类号： H05K1/14
CPC分类号： H01L25/105 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/3511
摘要： A package stack may include a first package and a second package. The first package may have an IC chip with an active surface and a back surface. The active surface may be connected to a first major surface of a first circuit substrate. The second package may include a second IC chip with an active surface and a back surface. The back surface of the second IC chip may be attached to a first major surface of a second circuit substrate and the active surface of the second IC chip may be electrically connected to the first major surface of the second circuit substrate. The first package may be stacked on the second package so that the active surface of the second package may be electrically connected to a second major surface of the first circuit substrate of the first package. A method may involve providing a first package having a first IC chip and a first circuit substrate and providing a second package having a second IC chip and a second circuit substrate. The first and the second packages may be stacked so that the active surface of the second IC may face and be electrically connected to a major surface of the first circuit substrate.
摘要翻译：包装堆叠可以包括第一包装和第二包装。第一封装可以具有带有活性表面和背面的IC芯片。有源表面可以连接到第一电路基板的第一主表面。第二封装可以包括具有有源表面和后表面的第二IC芯片。第二IC芯片的背面可以附接到第二电路基板的第一主表面，并且第二IC芯片的有源表面可以电连接到第二电路基板的第一主表面。第一封装可以堆叠在第二封装上，使得第二封装的有源表面可以电连接到第一封装的第一电路基板的第二主表面。一种方法可以包括提供具有第一IC芯片和第一电路基板的第一封装，并提供具有第二IC芯片和第二电路基板的第二封装。可以堆叠第一和第二封装，使得第二IC的有源表面可以面对并且电连接到第一电路基板的主表面。

8. 发明申请

US20060008948A1 Method of processing a semiconductor wafer for manufacture of semiconductor device 失效
标题翻译：用于制造半导体器件的半导体晶片的处理方法
公开(公告)号：US20060008948A1
公开(公告)日：2006-01-12
申请号：US11172689
申请日：2005-06-30
申请人： Dae-Sang Chun , Jae-Hong Kim , Heui-Seog Kim , Jong-Keun Jeon , Wha-Su Sin
发明人： Dae-Sang Chun , Jae-Hong Kim , Heui-Seog Kim , Jong-Keun Jeon , Wha-Su Sin
IPC分类号： H01L21/44
CPC分类号： H01L21/78 , H01L21/6835 , H01L2221/6834 , H01L2221/68354 , H01L2221/68368
摘要： A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface. The method includes forming grooves of a predetermined depth on the second surface on which circuit patterns are formed, attaching a first surface of a protective tape to the second surface on which the grooves are formed, attaching a carrier tape to a second surface of the protective tape opposite to the first surface of the protective tape so that the first surface of the semiconductor wafer can be oriented upward, removing the first surface of the semiconductor wafer by a predetermined thickness and dividing the semiconductor wafer into chips by the grooves, and supplying each chip to a die bonder in the state where the first surface of the of the chip is oriented upward. Only one kind of die bonder is needed. A UV-type tape is not required.
摘要翻译：一种处理具有与第一表面相对的第一表面和第二表面的半导体晶片的方法。该方法包括在其上形成有电路图案的第二表面上形成预定深度的凹槽，将保护带的第一表面附接到其上形成有凹槽的第二表面，将载带附着到保护层的第二表面上带，使得半导体晶片的第一表面可以向上取向，将半导体晶片的第一表面除去预定厚度，并通过凹槽将半导体晶片分成芯片，并且将每个在芯片的第一表面朝向上方的状态下的芯片接合器。只需要一种管芯焊接机。不需要UV型胶带。

9. 发明授权

US07713788B2 Method of manufacturing semiconductor package using redistribution substrate 有权
标题翻译：使用再分布基板制造半导体封装的方法
公开(公告)号：US07713788B2
公开(公告)日：2010-05-11
申请号：US12197067
申请日：2008-08-22
申请人： Jun-Young Ko , Dae-Sang Chan , Heui-Seog Kim , Wha-Su Sin , Jae-Yong Park
发明人： Jun-Young Ko , Dae-Sang Chan , Heui-Seog Kim , Wha-Su Sin , Jae-Yong Park
IPC分类号： H01L21/44
CPC分类号： H01L23/3128 , H01L23/49833 , H01L23/5389 , H01L24/24 , H01L25/0657 , H01L2224/24226 , H01L2224/82039 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01029 , H01L2924/01033 , H01L2924/15311
摘要： An inexpensive method of manufacturing a semiconductor package using a redistribution substrate that is relatively thin. The method includes: attaching a semiconductor chip to a redistribution substrate; attaching the redistribution substrate to which the semiconductor chip is attached to a printed circuit board; removing a support substrate of the redistribution substrate; forming via holes to expose a bond pad of the semiconductor chip and a bond finger of the printed circuit board; and filling the via holes with a conductive material. Meanwhile, a redistribution substrate to which at least one other semiconductor chip may be mounted on the redistribution substrate.
摘要翻译：使用相对薄的再分布基板制造半导体封装的廉价方法。该方法包括：将半导体芯片附接到再分布基板; 将安装有半导体芯片的再分布基板附着到印刷电路板上; 去除所述再分布基板的支撑基板; 形成通孔以暴露所述半导体芯片的接合焊盘和所述印刷电路板的接合指状物; 并用导电材料填充通孔。同时，可以将至少一个其它半导体芯片安装在再分布基板上的再分布基板。

10. 发明申请

US20090200362A1 METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：制造半导体封装的方法
公开(公告)号：US20090200362A1
公开(公告)日：2009-08-13
申请号：US12369257
申请日：2009-02-11
申请人： Ky-Hyun JUNG , Jae-Yong Park , Heui-Seog Kim , Wha-Su Sin , Jung-Hyeon Kim
发明人： Ky-Hyun JUNG , Jae-Yong Park , Heui-Seog Kim , Wha-Su Sin , Jung-Hyeon Kim
IPC分类号： B23K31/02 , B23K1/20
CPC分类号： B23K1/0016 , B23K1/0053 , B23K1/008 , B23K1/206 , B23K2101/42 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L25/105 , H01L2224/05568 , H01L2224/05573 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01077 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19043 , H01L2924/3651 , H05K3/3436 , H05K3/3463 , H05K2201/10734 , H01L2224/05599
摘要： In a lead-free solder, a semiconductor package and a method of manufacturing the semiconductor package, the lead-free solder includes about 3.5 percent by weight to about 6 percent by weight of silver, about 0.05 percent by weight to about 0.5 percent by weight of copper and a remainder of tin. The lead-free solder is employed in the semiconductor package. The lead-free solder has high impact resistance and high heat resistance to reduce failures of the semiconductor package.
摘要翻译：在无铅焊料，半导体封装和半导体封装的制造方法中，无铅焊料包括约3.5重量％至约6重量％的银，约0.05重量％至约0.5重量％的铜和余下的锡。在半导体封装中采用无铅焊料。无铅焊料具有高抗冲击性和高耐热性，以减少半导体封装的故障。

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