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1. 发明申请

US20110165750A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES 审中-公开
标题翻译：制造包括结构在内的半导体器件的方法
公开(公告)号：US20110165750A1
公开(公告)日：2011-07-07
申请号：US12984940
申请日：2011-01-05
申请人： Jun-Kyu Yang , Young-Geun Park , Ki-Hyun Hwang , Han-Mei Choi , Chan-Jin Park
发明人： Jun-Kyu Yang , Young-Geun Park , Ki-Hyun Hwang , Han-Mei Choi , Chan-Jin Park
IPC分类号： H01L21/336
CPC分类号： H01L21/7682 , H01L21/02164 , H01L21/02266 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns.
摘要翻译：在制造半导体器件的方法中，多个彼此间隔开的栅极结构和氧化物层图案。执行使用氧化物层图案作为溅射靶的溅射工艺来将相邻栅极结构上的氧化物层图案彼此连接，使得在栅极结构之间形成间隙。通过控制氧化物层图案的厚度，使间隙的体积均匀地形成为具有期望的体积。

2. 发明授权

US08426304B2 Methods of manufacturing a vertical type semiconductor device 有权
标题翻译：制造垂直型半导体器件的方法
公开(公告)号：US08426304B2
公开(公告)日：2013-04-23
申请号：US13241316
申请日：2011-09-23
申请人： Dong-Chul Yoo , Chan-Jin Park , Ki-Hyun Hwang , Han-Mei Choi , Joon-Suk Lee
发明人： Dong-Chul Yoo , Chan-Jin Park , Ki-Hyun Hwang , Han-Mei Choi , Joon-Suk Lee
IPC分类号： H01L21/4763
CPC分类号： H01L27/11582 , H01L27/105 , H01L27/11573 , H01L27/11575
摘要： Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.
摘要翻译：制造半导体器件的方法包括在衬底的第一区域中形成停止层图案。第一模具结构形成在与第一区域相邻的基板的第二区域中。第一模具结构包括交替堆叠的第一牺牲图案和第一层间图案。在第一模具结构和止挡层图案上形成第二模具结构。第二模具结构包括交替堆叠的第二牺牲图案和第二层间图案。第二模具结构部分地覆盖止挡层图案。形成通道图案并通过第一模具结构和第二模具结构。

3. 发明授权

US08822287B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08822287B2
公开(公告)日：2014-09-02
申请号：US13313754
申请日：2011-12-07
申请人： Hyo-Jung Kim , Ki-hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
发明人： Hyo-Jung Kim , Ki-hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
IPC分类号： H01L21/336
CPC分类号： H01L21/31053 , H01L21/3212 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.
摘要翻译：制造半导体器件的方法包括在第一区域中形成集成结构和第一停止层图案。形成第一绝缘层和第二阻挡层。通过部分蚀刻第一区域中的第二阻挡层和第一绝缘中间层来形成第二初步绝缘中间层。执行第一次抛光以去除突出部分。执行第二抛光以暴露第一和第二停止层图案。

4. 发明申请

US20120149185A1 Methods Of Manufacturing Semiconductor Devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120149185A1
公开(公告)日：2012-06-14
申请号：US13313754
申请日：2011-12-07
申请人： Hyo-Jung Kim , Ki-Hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
发明人： Hyo-Jung Kim , Ki-Hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
IPC分类号： H01L21/3205 , H01L21/311
CPC分类号： H01L21/31053 , H01L21/3212 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.
摘要翻译：制造半导体器件的方法包括在第一区域中形成集成结构和第一停止层图案。形成第一绝缘层和第二阻挡层。通过部分蚀刻第一区域中的第二阻挡层和第一绝缘中间层来形成第二初步绝缘中间层。执行第一次抛光以去除突出部分。执行第二抛光以暴露第一和第二停止层图案。

5. 发明申请

US20120115309A1 Methods of Manufacturing a Vertical Type Semiconductor Device 有权
标题翻译：制造垂直型半导体器件的方法
公开(公告)号：US20120115309A1
公开(公告)日：2012-05-10
申请号：US13241316
申请日：2011-09-23
申请人： Dong-Chul Yoo , Chan-Jin Park , Ki-Hyun Hwang , Han-Mei Choi , Joon-Suk Lee
发明人： Dong-Chul Yoo , Chan-Jin Park , Ki-Hyun Hwang , Han-Mei Choi , Joon-Suk Lee
IPC分类号： H01L21/28
CPC分类号： H01L27/11582 , H01L27/105 , H01L27/11573 , H01L27/11575
摘要： Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.
摘要翻译：制造半导体器件的方法包括在衬底的第一区域中形成停止层图案。第一模具结构形成在与第一区域相邻的基板的第二区域中。第一模具结构包括交替堆叠的第一牺牲图案和第一层间图案。在第一模具结构和止挡层图案上形成第二模具结构。第二模具结构包括交替堆叠的第二牺牲图案和第二层间图案。第二模具结构部分地覆盖止挡层图案。形成通道图案并通过第一模具结构和第二模具结构。

6. 发明授权

US09153577B2 Nonvolatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09153577B2
公开(公告)日：2015-10-06
申请号：US13537454
申请日：2012-06-29
申请人： Chan-Jin Park
发明人： Chan-Jin Park
IPC分类号： H01L21/8239 , H01L27/06 , H01L27/10 , H01L27/24 , H01L45/00
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： Provided is a method of fabricating a nonvolatile memory device. The method of fabricating a nonvolatile memory device, the method comprising: sequentially stacking a first interlayer insulating film, a first sacrificial film, a second interlayer insulating film, and a second sacrificial film on a semiconductor substrate; forming a first penetrating portion, which exposes a region of a top surface of the semiconductor substrate, by etching the first and second interlayer insulating films and the first and second sacrificial films; forming an epitaxial layer on the exposed region of the top surface of the semiconductor substrate in the first penetrating portion by epitaxial growth; forming a first electrode, which contacts a resistance change film and the epitaxial layer, in the first penetrating portion; exposing regions of side surfaces of the epitaxial layer by removing the first epitaxial film; forming an insulating film inside the exposed regions of the side surfaces of the epitaxial layer; and forming a second electrode on the exposed regions of the side surfaces of the epitaxial layer.
摘要翻译：提供一种制造非易失性存储器件的方法。一种制造非易失性存储器件的方法，该方法包括：在半导体衬底上依次层叠第一层间绝缘膜，第一牺牲膜，第二层间绝缘膜和第二牺牲膜; 通过蚀刻所述第一和第二层间绝缘膜和所述第一和第二牺牲膜，形成暴露所述半导体衬底的顶表面的区域的第一穿透部分; 通过外延生长在第一穿透部分的半导体衬底的顶表面的暴露区域上形成外延层; 在第一穿透部分中形成接触电阻变化膜和外延层的第一电极; 通过去除第一外延膜来暴露外延层的侧表面的区域; 在外延层的侧表面的暴露区域内形成绝缘膜; 以及在所述外延层的侧表面的暴露区域上形成第二电极。

7. 发明授权

US08525247B2 Non-volatile memory device having variable resistance element 有权
标题翻译：具有可变电阻元件的非易失性存储器件
公开(公告)号：US08525247B2
公开(公告)日：2013-09-03
申请号：US13462844
申请日：2012-05-03
申请人： Chan-Jin Park , Hyun-Su Ju , In-Gyu Baek
发明人： Chan-Jin Park , Hyun-Su Ju , In-Gyu Baek
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L23/053 , H01L23/12 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.
摘要翻译：非易失性存储器件包括下成型层，下成型层上的水平互连线，水平互连线上的上成型层，垂直穿过上成型层，水平互连线和下成型件的柱层和介于柱和成型层之间的缓冲层。该装置还包括可变电阻材料和插在支柱和水平互连线之间的二极管层。

8. 发明授权

US08796662B2 Semiconductor devices with vertical structure including data storage layer or pattern 有权
标题翻译：具有垂直结构的半导体器件包括数据存储层或图案
公开(公告)号：US08796662B2
公开(公告)日：2014-08-05
申请号：US13565830
申请日：2012-08-03
申请人： Seong-Ho Song , Chan-Jin Park , In-Gyu Baek
发明人： Seong-Ho Song , Chan-Jin Park , In-Gyu Baek
IPC分类号： H01L29/06
CPC分类号： H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.
摘要翻译：半导体器件包括第一水平成型图案，设置在第一水平成型图案上的水平电极图案和设置在水平电极图案上的第二水平成型图案。垂直结构延伸穿过水平图案。垂直结构包括垂直电极图案，插入在垂直电极图案和水平图案之间的数据存储图案，插入在数据存储图案和第一模制图案之间的第一缓冲图案和插入在数据存储器之间的第二缓冲图案图案和第二模制图案并且与第一缓冲图案间隔开。

9. 发明申请

US20080128757A1 Non-volatile memory devices including vertical channels, methods of operating, and methods of fabricating the same 有权
标题翻译：包括垂直通道的非易失性存储器件，操作方法及其制造方法
公开(公告)号：US20080128757A1
公开(公告)日：2008-06-05
申请号：US11999135
申请日：2007-12-04
申请人： Soo-Doo Chae , Chung-Woo Kim , Chan-Jin Park , Jeong-Hee Han , Byung-Gook Park , Il-Han Park
发明人： Soo-Doo Chae , Chung-Woo Kim , Chan-Jin Park , Jeong-Hee Han , Byung-Gook Park , Il-Han Park
IPC分类号： G11C11/407 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0416 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A flash memory device can include a semiconductor pin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor pin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor pin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.
摘要翻译：闪速存储器件可以包括从第一导电类型的半导体衬底突出以在一个方向上延伸的半导体引脚，分别设置到半导体引脚的上部和下部的第一掺杂层和第二掺杂层，彼此垂直间隔开，第一和第二掺杂层具有第二导电类型，并且多个字线在半导体引脚的顶部和侧壁上延伸以与该方向相交。字线与第一掺杂层和第二掺杂层重叠以具有垂直沟道。

10. 发明授权

US09159727B2 Nonvolatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09159727B2
公开(公告)日：2015-10-13
申请号：US13537588
申请日：2012-06-29
申请人： Chan-Jin Park
发明人： Chan-Jin Park
IPC分类号： H01L21/02 , H01L27/10 , H01L27/24 , H01L45/00
CPC分类号： H01L27/101 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： Provided are a nonvolatile memory device and a method for fabricating the same. The method includes sequentially stacking on a semiconductor substrate a first interlayer dielectric film, a first sacrificial layer, a second interlayer dielectric film, and a second sacrificial layer, forming a resistance variable layer and a first electrode penetrating the first and second interlayer dielectric films and the first and second sacrificial layers, forming an upper trench by removing a top portion of the first electrode, filling the upper trench with a channel layer, exposing a portion of a side surface of the resistance variable layer by removing the second sacrificial layer, forming an insulation layer within the channel layer, and forming a second electrode on the exposed resistance variable layer.
摘要翻译：提供一种非易失性存储器件及其制造方法。该方法包括在半导体衬底上依次堆叠第一层间电介质膜，第一牺牲层，第二层间电介质膜和第二牺牲层，形成电阻变化层和穿透第一和第二层间电介质膜的第一电极，以及所述第一牺牲层和所述第二牺牲层通过去除所述第一电极的顶部而形成上沟槽，用沟道层填充所述上沟槽，通过去除所述第二牺牲层暴露所述电阻可变层的侧表面的一部分，形成沟道层内的绝缘层，并且在暴露的电阻变化层上形成第二电极。

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