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1. 发明授权

US07742118B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07742118B2
公开(公告)日：2010-06-22
申请号：US11690563
申请日：2007-03-23
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

2. 发明申请

US20080252806A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20080252806A1
公开(公告)日：2008-10-16
申请号：US12141623
申请日：2008-06-18
申请人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

3. 发明授权

US07403240B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07403240B2
公开(公告)日：2008-07-22
申请号：US11741470
申请日：2007-04-27
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136 , G02F1/1335
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

4. 发明申请

US20070200981A1 Thin Film Transistor Array Panel and Manufacturing Method Thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20070200981A1
公开(公告)日：2007-08-30
申请号：US11741470
申请日：2007-04-27
申请人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung SOUK , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/1335 , G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

5. 发明申请

US20070190706A1 Thin Film Transistor Array Panel And Manufacturing Method Thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20070190706A1
公开(公告)日：2007-08-16
申请号：US11690563
申请日：2007-03-23
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： H01L21/84
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

6. 发明授权

US08068188B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08068188B2
公开(公告)日：2011-11-29
申请号：US12141623
申请日：2008-06-18
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/1343 , G02F1/136
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

7. 发明授权

US07265799B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07265799B2
公开(公告)日：2007-09-04
申请号：US10759389
申请日：2004-01-16
申请人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
发明人： Jun-Hyung Souk , Jeong-Young Lee , Jong-Soo Yoon , Kwon-Young Choi , Bum-Ki Baek
IPC分类号： G02F1/136 , H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括：在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂，比所述第一部分更厚且位于所述漏极上的第二部分，以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模，将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。

8. 发明授权

US07320906B2 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US07320906B2
公开(公告)日：2008-01-22
申请号：US10922343
申请日：2004-08-19
申请人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
发明人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
IPC分类号： H01L21/84
CPC分类号： H01L29/41733 , H01L27/124
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

9. 发明申请

US20050082535A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050082535A1
公开(公告)日：2005-04-21
申请号：US10926719
申请日：2004-08-26
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1339 , G02F1/1368 , G03C1/85 , G03C5/00 , G09F9/30 , H01L21/00 , H01L21/336 , H01L29/786
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

10. 发明授权

US07566906B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07566906B2
公开(公告)日：2009-07-28
申请号：US11958230
申请日：2007-12-17
申请人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , San-Jin Jeon
发明人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , San-Jin Jeon
IPC分类号： H01L29/04
CPC分类号： H01L29/41733 , H01L27/124
摘要： A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上的半导体层; 形成在所述半导体层上的多个欧姆接触; 源极和漏极形成在欧姆接触上; 形成在源电极和漏电极上的钝化层，具有露出漏电极的一部分的第一接触孔和露出半导体层的第一部分并且具有与源电极和漏电极的边缘重合的边缘的开口; 以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。

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