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1. 发明申请

US20150056805A1 METHODS OF FORMING SEMICONDUCTOR DEVICE USING BOWING CONTROL LAYER 有权
标题翻译：使用控制层形成半导体器件的方法
公开(公告)号：US20150056805A1
公开(公告)日：2015-02-26
申请号：US14247635
申请日：2014-04-08
申请人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
发明人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L27/10852 , H01L28/90
摘要： A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.
摘要翻译：在中间层上形成弯曲控制图案。在弓形控制层上形成硬掩模图案。硬掩模图案具有第一开口，并且弯曲控制图案具有第二开口。第三开口穿过中间层并连接到第二开口。弯曲控制图案包括在第二开口的下端上的第一边缘和第二边缘，以及在第二开口的上端上的第三边缘。当第一边缘上的第一点，第二边缘上的第二点和通过第三边缘的水平线上的第三点被限定时，从第一点到第二点的第一侧之间的相交角，以及从第二点到第三点的第二侧为约50°至约80°。

2. 发明授权

US08420453B2 Method of forming active region structure 有权
标题翻译：形成有源区结构的方法
公开(公告)号：US08420453B2
公开(公告)日：2013-04-16
申请号：US12801074
申请日：2010-05-20
申请人： Jun-Ho Yoon , Byeong-Soo Kim , Kyoung-Sub Shin , Hong Cho , Hyung-Yong Kim
发明人： Jun-Ho Yoon , Byeong-Soo Kim , Kyoung-Sub Shin , Hong Cho , Hyung-Yong Kim
IPC分类号： H01L21/82
CPC分类号： H01L21/308 , H01L21/76229 , H01L27/0207 , H01L27/1052 , H01L27/10894 , H01L27/11526
摘要： A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.
摘要翻译：形成有源区结构的方法包括制备包括单元阵列区域和外围电路区域的半导体衬底，在半导体衬底的单元阵列区域中形成初级电池活性区域，并在初级电池活性区域中形成电池活性区域以及半导体衬底的外围电路区域中的至少一个外围有源区域，使得初步电池活性区域，电池活性区域和至少一个外围有源区域与半导体衬底一体地形成并从半导体基质。

3. 发明授权

US09093500B2 Methods of forming semiconductor device using bowing control layer 有权
标题翻译：使用弯曲控制层形成半导体器件的方法
公开(公告)号：US09093500B2
公开(公告)日：2015-07-28
申请号：US14247635
申请日：2014-04-08
申请人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
发明人： Jae-Hong Park , Min-Joon Park , Jun-Ho Yoon , Gyung-Jin Min , Jin-Young Park , Je-Woo Han
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L27/10852 , H01L28/90
摘要： A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.
摘要翻译：在中间层上形成弯曲控制图案。在弓形控制层上形成硬掩模图案。硬掩模图案具有第一开口，并且弯曲控制图案具有第二开口。第三开口穿过中间层并连接到第二开口。弯曲控制图案包括在第二开口的下端上的第一边缘和第二边缘，以及在第二开口的上端上的第三边缘。当第一边缘上的第一点，第二边缘上的第二点和通过第三边缘的水平线上的第三点被限定时，从第一点到第二点的第一侧之间的相交角，以及从第二点到第三点的第二侧为约50°至约80°。

4. 发明授权

US08563371B2 Method of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US08563371B2
公开(公告)日：2013-10-22
申请号：US13216051
申请日：2011-08-23
申请人： Kyung-Yub Jeon , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
发明人： Kyung-Yub Jeon , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
IPC分类号： H01L21/84 , H01L21/00 , H01L21/8238 , H01L21/461 , H01L21/302
CPC分类号： H01L21/28273 , H01L21/823456 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.
摘要翻译：提供一种形成半导体器件的方法。该方法可以包括在半导体衬底上形成第一绝缘层。可以在第一绝缘层上形成第一多晶硅层。可以在第一多晶硅层上形成第二绝缘层。可以在第二绝缘层上形成第二多晶硅层。可以在第二多晶硅层上形成掩模图案。可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层，以形成露出第二绝缘层的一部分的第二多晶硅图案。第二多晶硅图案的侧壁可以包括第一非晶区域。第一非晶区域可以通过第一次重结晶过程结晶。可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。

5. 发明授权

US08426274B2 Method of forming recess and method of manufacturing semiconductor device having the same 有权
标题翻译：形成凹部的方法和制造其的半导体器件的制造方法
公开(公告)号：US08426274B2
公开(公告)日：2013-04-23
申请号：US12861247
申请日：2010-08-23
申请人： Jun-Ho Yoon , Kyoung-Sub Shin , Sung-Sam Lee , Kung-Hyon Nam , Hong Cho , Joon-Seok Moon
发明人： Jun-Ho Yoon , Kyoung-Sub Shin , Sung-Sam Lee , Kung-Hyon Nam , Hong Cho , Joon-Seok Moon
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/02238 , H01L21/3065 , H01L29/66621
摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.
摘要翻译：示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。该方法包括形成在衬底中限定有源区的场区域。有源区在衬底中沿第一方向延伸。所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍牺牲氧化层。

6. 发明申请

US20120064709A1 METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20120064709A1
公开(公告)日：2012-03-15
申请号：US13216051
申请日：2011-08-23
申请人： Kyung-Yub JEON , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
发明人： Kyung-Yub JEON , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , H01L21/823456 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating to layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.
摘要翻译：提供一种形成半导体器件的方法。该方法可以包括在半导体衬底上形成第一绝缘层。可以在第一绝缘层上形成第一多晶硅层。可以在第一多晶硅层上形成第二绝缘层。可以在第二绝缘层上形成第二多晶硅层。可以在第二多晶硅层上形成掩模图案。可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层，以形成暴露第二绝缘层的一部分的第二多晶硅图案。第二多晶硅图案的侧壁可以包括第一非晶区域。第一非晶区域可以通过第一次重结晶过程结晶。可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。

7. 发明申请

US20060143321A1 Apparatus and method for managing peripheral device using auto-generated metadata 审中-公开
标题翻译：使用自动生成元数据管理外围设备的装置和方法
公开(公告)号：US20060143321A1
公开(公告)日：2006-06-29
申请号：US11290443
申请日：2005-12-01
申请人： Jun-Ho Yoon
发明人： Jun-Ho Yoon
IPC分类号： G06F3/00
CPC分类号： H04L67/125
摘要： A peripheral device managing apparatus using auto-generated metadata and method of using the same are provided. The peripheral device managing apparatus includes a plurality of peripheral devices for generating execution data by executing a function of the peripheral device, and generating metadata which includes identification information of the execution data, a plurality of peripheral device controlling units for respectively controlling the peripheral devices through a network, and generating management data by adding the metadata to the execution data, and a peripheral device managing unit for storing the generated management data, and retrieving management data which meets a predetermined search condition out of the management data. Accordingly, a plurality of peripheral devices and a plurality of peripheral device controlling units can be efficiently managed.
摘要翻译：提供了使用自动生成元数据的外围设备管理装置及其使用方法。外围设备管理设备包括多个外围设备，用于通过执行外围设备的功能来生成执行数据，并且生成包括执行数据的识别信息的元数据，多个外围设备控制单元，用于分别控制外围设备通过网络，以及通过将元数据添加到执行数据来生成管理数据;以及外围设备管理单元，用于存储生成的管理数据，以及从管理数据中检索满足预定搜索条件的管理数据。因此，可以有效地管理多个外围设备和多个外围设备控制单元。

8. 发明申请

US20110284163A1 PLASMA PROCESSING APPARATUS 审中-公开
标题翻译：等离子体加工设备
公开(公告)号：US20110284163A1
公开(公告)日：2011-11-24
申请号：US13086475
申请日：2011-04-14
申请人： Jun-Ho Yoon , Kyoung-Sub Shin , Woo-Seok Kim , Dong-Kwon Kim , Hyung-Yong Kim , Yong-Ho Jeon
发明人： Jun-Ho Yoon , Kyoung-Sub Shin , Woo-Seok Kim , Dong-Kwon Kim , Hyung-Yong Kim , Yong-Ho Jeon
IPC分类号： H01L21/00 , C23F1/08
CPC分类号： H01L21/67069 , H01J37/32935 , H01J37/32972
摘要： A plasma processing apparatus includes a chamber for processing a substrate. A plasma generator is provided to generate plasma within the chamber. A window is provided in a sidewall of the chamber, and the window transmits light from the plasma within the chamber. A photocatalytic layer is provided on an inner surface of the window such that the photocatalytic layer is activated as a result of exposure to light from the plasma to decompose a residual product on the inner surface of the window.
摘要翻译：等离子体处理装置包括用于处理基板的室。提供等离子体发生器以在腔室内产生等离子体。窗口设置在室的侧壁中，并且窗口从腔室内的等离子体透射光。在窗的内表面上提供光催化层，使得光催化层由于暴露于等离子体的光而被激活，从而在窗的内表面上分解残留产物。

9. 发明申请

US20090042396A1 METHODS OF FORMING SEMICONDUCTOR DEVICES USING SELECTIVE ETCHING OF AN ACTIVE REGION THROUGH A HARDMASK 有权
标题翻译：通过HARDMASK选择性蚀刻活性区域形成半导体器件的方法
公开(公告)号：US20090042396A1
公开(公告)日：2009-02-12
申请号：US12187895
申请日：2008-08-07
申请人： Heung-Sik Park , Jun-Ho Yoon , Cheol-Kyu Lee , Joon-Soo Park
发明人： Heung-Sik Park , Jun-Ho Yoon , Cheol-Kyu Lee , Joon-Soo Park
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/3065 , H01L29/4236 , H01L29/66621
摘要： A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.
摘要翻译：提供一种制造半导体器件的方法。该方法可以包括在其上限定有源区和隔离区的衬底上形成包括下硬掩模膜和上硬掩模膜的硬掩模膜，并对硬掩模膜进行构图以提供部分暴露有源区的硬掩模图案和隔离地区。可以使用硬掩模图案作为蚀刻掩模将蚀刻剂施加到有源和隔离区域，以在衬底的有源区域中形成沟槽，同时避免基本上蚀刻暴露于蚀刻剂的隔离区域，并且可以在栅极上形成栅极沟。

10. 发明授权

US08815697B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08815697B2
公开(公告)日：2014-08-26
申请号：US13478450
申请日：2012-05-23
申请人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
发明人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
IPC分类号： H01L21/3213 , H01L27/108 , H01L21/285
CPC分类号： H01L28/90 , H01L27/10852
摘要： Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
摘要翻译：提供一种制造具有电容器的半导体器件的方法。该方法包括形成复合层，包括顺序地堆叠在第一至第n牺牲层和第一至第n支撑层上的交替层上的衬底上。形成贯穿复合层的多个开口。在多个开口中形成下电极。去除第一至第n牺牲层的至少部分以限定在多个开口中相邻的开口和形成在其中的下电极之间延伸的下电极的支撑结构，支撑结构包括第一至第n支撑层和间隙在第一至第n个支撑层中相邻的第一至第n个牺牲层已被去除之间的区域。在下电极上形成介电层，在电介质层上形成上电极。

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