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1. 发明申请

US20080072184A1 Method of Achieving Timing Closure in Digital Integrated Circuits by Optimizing Individual Macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的定时闭合的方法
公开(公告)号：US20080072184A1
公开(公告)日：2008-03-20
申请号：US11942034
申请日：2007-11-19
申请人： Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
发明人： Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

2. 发明申请

US20060150127A1 Method of achieving timing closure in digital integrated circuits by optimizing individual macros 审中-公开
标题翻译：通过优化单个宏来实现数字集成电路中的时序闭合的方法
公开(公告)号：US20060150127A1
公开(公告)日：2006-07-06
申请号：US11296780
申请日：2005-12-07
申请人： Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
发明人： Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

3. 发明申请

US20060206845A1 Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect 有权
标题翻译：混合线性线模型方法来调整具有RC互连的电路的晶体管宽度
公开(公告)号：US20060206845A1
公开(公告)日：2006-09-14
申请号：US11077043
申请日：2005-03-10
申请人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey Soreff , Patrick Williams , David Hathaway
发明人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey Soreff , Patrick Williams , David Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068
摘要： A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent “de-tuning” that typically occurs when all Rs are shorted, ‘wire-adjusts’ are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.
摘要翻译：描述了用于调谐由RC互连链接的电路的晶体管宽度的混合线性线模型。在调谐过程中，该方法使用两个嵌入式模拟器，其中包含电阻（Rs）。面向计时的模拟器仅用于包含所有Rs的原始网表的时序目的。然后，一个面向梯度的模拟器仅在修改后的网表上运行，所有的Rs都已经短路，并在调谐器的迭代循环内计算梯度。目前的混合方法实现了计算速度的显着提高。面向时序的模拟器只需要具有Rs的时间网络列表即可快速准确，但无法有效地计算渐变。梯度导向模拟器有效地计算梯度，但在Rs的存在下不能这样做。为了防止所有Rs短路时通常发生的“去调谐”，提供“线调整”，使得在短路网表上使用面向梯度的模拟器的初始定时结果与使用定时模型的原始网表上的定时结果相匹配。这允许优化器最初感测正确的关键定时路径集合，并且更重要的是，它允许线路调整跟踪改变的晶体管宽度，以在迭代期间引导优化器直到实现收敛。

4. 发明申请

US20050066297A1 System and method for correlated process pessimism removal for static timing analysis 失效
标题翻译：静态时序分析相关过程悲观消除的系统和方法
公开(公告)号：US20050066297A1
公开(公告)日：2005-03-24
申请号：US10665273
申请日：2003-09-18
申请人： Kerim Kalafala , Peihua Qi , David Hathaway , Alexander Suess , Chandramouli Visweswariah
发明人： Kerim Kalafala , Peihua Qi , David Hathaway , Alexander Suess , Chandramouli Visweswariah
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.
摘要翻译：描述了静态时序分析中消除悲观情绪的方法。延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。分析以路径为基础进行。通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。

5. 发明申请

US20070061771A1 METHOD FOR RETICLE SHAPES ANALYSIS AND CORRECTION 失效
标题翻译：用于形式分析和校正的方法
公开(公告)号：US20070061771A1
公开(公告)日：2007-03-15
申请号：US11162586
申请日：2005-09-15
申请人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson , Tad Wilder
发明人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson , Tad Wilder
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
摘要翻译：一种多光栅掩模版设计的掩模版设计校正和电参数提取的方法。该方法包括：选择多小区掩模版设计的小区设计的子集，小区设计子集的每个小区设计具有相应的处理形状，用于确定相应小区设计位置的小区设计子集的每个小区设计的相应形状; 基于每个相应形状的相应单元设计位置，确定每个单元设计的所有对应形状的共同形状处理规则; 以及仅对单元设计的子集的单个单元设计执行相应形状的形状处理，以生成用于所述单元设计的子集的结果数据。还有一种包括计算机可读程序代码的计算机可用介质，其具有适于实现掩模版设计校正和电提取的方法的算法。

6. 发明申请

US20060265684A1 THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT 有权
标题翻译：使用冗余路由增加VLSI布局的可靠性
公开(公告)号：US20060265684A1
公开(公告)日：2006-11-23
申请号：US10908593
申请日：2005-05-18
申请人： Markus Buehler , John Cohn , David Hathaway , Jason Hibbeler , Juergen Koehl
发明人： Markus Buehler , John Cohn , David Hathaway , Jason Hibbeler , Juergen Koehl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.
摘要翻译：公开了一种将冗余路径插入到集成电路中的方法和系统。特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用交替路线。第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。

7. 发明申请

US20080074147A1 WIRING OPTIMIZATIONS FOR POWER 有权
标题翻译：电力接线优化
公开(公告)号：US20080074147A1
公开(公告)日：2008-03-27
申请号：US11952544
申请日：2007-12-07
申请人： John Cohn , Alvar Dean , Amir Farrahi , David Hathaway , Thomas Lepsic , Jagannathan Narasimhan , Scott Tetreault , Sebastian Ventrone
发明人： John Cohn , Alvar Dean , Amir Farrahi , David Hathaway , Thomas Lepsic , Jagannathan Narasimhan , Scott Tetreault , Sebastian Ventrone
IPC分类号： H03K19/00 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.
摘要翻译：一种用于设计电气布线结构的电气布线结构和计算机系统。电气配线结构包括电线对。线对包括第一线和第二线。第二根电线被预定为三态。线对具有不小于预先选择的最小相同方向切换概率phi，SD，MIN或/或具有相同方向的切换概率，每时钟周期每个时钟周期的相反方向切换概率Φ不小于预先选择的最小相对方向切换概率φi，MIN 。第一线和第二线满足至少一个数学关系，其涉及公平和平坦，其中，W SPACING 被定义为第一线和第二线，以及公共被定义为第一线和第二线的公共行程长度。

8. 发明申请

US20070226667A1 STATIC TIMING SLACKS ANALYSIS AND MODIFICATION 有权
标题翻译：静态时序分析与修改
公开(公告)号：US20070226667A1
公开(公告)日：2007-09-27
申请号：US11277385
申请日：2006-03-24
申请人： Thomas Chadwick , Margaret Charlebois , David Hathaway , Jason Rotella , Douglas Stout , Ivan Wemple
发明人： Thomas Chadwick , Margaret Charlebois , David Hathaway , Jason Rotella , Douglas Stout , Ivan Wemple
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

9. 发明申请

US20060247906A1 METHOD FOR ESTIMATING CLOCK JITTER FOR STATIC TIMING MEASUREMENTS OF MODELED CIRCUITS 审中-公开
标题翻译：用于估计建模电路静态时序测量的时钟抖动的方法
公开(公告)号：US20060247906A1
公开(公告)日：2006-11-02
申请号：US10908100
申请日：2005-04-27
申请人： John Austin , David Hathaway , Timothy Platt , Stephen Wyatt
发明人： John Austin , David Hathaway , Timothy Platt , Stephen Wyatt
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method in accordance with the invention for modeling period jitter for testing a modeled logic circuit. Clock signals can be derived from a phase lock loop having a voltage controlled oscillator for use to evaluate timing problems within a modeled circuit. An estimation of period jitter for the modeled clock signals can be made by considering the number of periods of the voltage controlled oscillator signal which generates the clock signal occurring within a test interval. By using the relationship as an index to a table, a value of period jitter may be obtained from a table which increases longer the timing interval being considered. Instructions for carrying out the steps of correcting intervals between clock signals used in static timing tests may be stored on a computer readable medium along with a table containing the amount of period jitter as a function of the number of VCO periods occurring within a testing period. The improved accuracy in period jitter estimation improves the reliability of static testing of modeled circuits.
摘要翻译：根据本发明的用于建模用于测试建模的逻辑电路的周期抖动的方法。时钟信号可以从具有压控振荡器的锁相环导出，用于评估建模的电路内的定时问题。可以通过考虑产生在测试间隔内发生的时钟信号的压控振荡器信号的周期数来进行建模时钟信号的周期抖动的估计。通过使用该关系作为表的索引，可以从考虑的时间间隔更长的表获得周期抖动的值。用于执行校正在静态定时测试中使用的时钟信号之间的时间间隔的步骤的指令可以与包含在测试周期内出现的VCO周期数的函数的周期抖动量的表一起存储在计算机可读介质上。周期抖动估计的改进精度提高了建模电路的静态测试的可靠性。

10. 发明申请

US20060190899A1 METHOD OF CLOCK TREE DISTRIBUTION GENERATION BY DETERMINING ALLOWED PLACEMENT REGIONS FOR CLOCKED ELEMENTS 有权
标题翻译：通过确定时钟元件的允许放置区域来生成时钟树分布方法
公开(公告)号：US20060190899A1
公开(公告)日：2006-08-24
申请号：US10905970
申请日：2005-01-28
申请人： William Migatz , Paul Campbell , David Hathaway , David Kung , Ruchir Puri , Louise Trevillyan
发明人： William Migatz , Paul Campbell , David Hathaway , David Kung , Ruchir Puri , Louise Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F1/10
摘要： A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.
摘要翻译：描述了一种方法，系统和程序产品，用于通过为集成电路中的一组时钟树叶元素中的每一个确定允许的布局区域来在集成电路上生成时钟分配网络。通过确定和相交不同约束下的一组子区域来生成该允许的放置区域，每个子区域标识其中放置时钟树叶元素的区域以满足相应的约束。确定子区域的约束包括松弛和拥挤约束形式的时间约束。在确定了允许的放置区域之后，时钟树叶元素被聚集，并且每个时钟树叶元素被放置在其允许的放置区域内的位置，这使得该聚类的一些成本函数最小化。

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