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1. 发明申请

US20060206845A1 Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect 有权
标题翻译：混合线性线模型方法来调整具有RC互连的电路的晶体管宽度
公开(公告)号：US20060206845A1
公开(公告)日：2006-09-14
申请号：US11077043
申请日：2005-03-10
申请人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey Soreff , Patrick Williams , David Hathaway
发明人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey Soreff , Patrick Williams , David Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068
摘要： A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent “de-tuning” that typically occurs when all Rs are shorted, ‘wire-adjusts’ are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.
摘要翻译：描述了用于调谐由RC互连链接的电路的晶体管宽度的混合线性线模型。在调谐过程中，该方法使用两个嵌入式模拟器，其中包含电阻（Rs）。面向计时的模拟器仅用于包含所有Rs的原始网表的时序目的。然后，一个面向梯度的模拟器仅在修改后的网表上运行，所有的Rs都已经短路，并在调谐器的迭代循环内计算梯度。目前的混合方法实现了计算速度的显着提高。面向时序的模拟器只需要具有Rs的时间网络列表即可快速准确，但无法有效地计算渐变。梯度导向模拟器有效地计算梯度，但在Rs的存在下不能这样做。为了防止所有Rs短路时通常发生的“去调谐”，提供“线调整”，使得在短路网表上使用面向梯度的模拟器的初始定时结果与使用定时模型的原始网表上的定时结果相匹配。这允许优化器最初感测正确的关键定时路径集合，并且更重要的是，它允许线路调整跟踪改变的晶体管宽度，以在迭代期间引导优化器直到实现收敛。

2. 发明申请

US20070234253A1 Multiple mode approach to building static timing models for digital transistor circuits 审中-公开
标题翻译：多模式方法来构建数字晶体管电路的静态时序模型
公开(公告)号：US20070234253A1
公开(公告)日：2007-10-04
申请号：US11391880
申请日：2006-03-29
申请人： Jeffrey Soreff , Philip Shephard , Fred Yang , Vasant Rao
发明人： Jeffrey Soreff , Philip Shephard , Fred Yang , Vasant Rao
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for building static models for transistor circuit design is described. This method includes performing an automatic timing model construction several times on certain problem CCCs, with different, typically incompatible sets of user-selected local information for each call. Each of the sets of local information is considered a mode of operation of the circuit, each generating a timing model for the mode of operation. The resulting set of timing models are placed in parallel in the overall timing graph for the digital design as a whole, which has the effect of making the timing analysis choose the most conservative numbers from across the set of parallel models.
摘要翻译：描述了一种用于构建晶体管电路设计的静态模型的方法和系统。该方法包括在某些问题CCC上执行多次自动定时模型构造，其中每个呼叫具有不同的，通常不兼容的用户选择的本地信息的集合。每组本地信息被认为是电路的操作模式，每一个都产生用于操作模式的定时模型。所得到的定时模型集合在整个数字设计的整体时序图中并行放置，这具有使得时序分析从整个并行模型集合中选择最保守的数字的效果。

3. 发明申请

US20060020443A1 Pulse waveform timing in EinsTLT templates 失效
标题翻译： EinsTLT模板中的脉冲波形定时
公开(公告)号：US20060020443A1
公开(公告)日：2006-01-26
申请号：US10897347
申请日：2004-07-22
申请人： Sang Lee , Vasant Rao , Jeffrey Soreff , James Warnock , David Winston
发明人： Sang Lee , Vasant Rao , Jeffrey Soreff , James Warnock , David Winston
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.
摘要翻译：本发明提供了模拟信号转换。产生电路特性。电路特性被加载到存储器中。模拟电路行为。捕获非前沿电路转换。这发生在软件中。

4. 发明授权

US07643981B2 Pulse waveform timing in EinsTLT templates 失效
标题翻译： EinsTLT模板中的脉冲波形定时
公开(公告)号：US07643981B2
公开(公告)日：2010-01-05
申请号：US10897347
申请日：2004-07-22
申请人： Sang Y. Lee , Vasant B. Rao , Jeffrey Soreff , James Warnock , David Winston
发明人： Sang Y. Lee , Vasant B. Rao , Jeffrey Soreff , James Warnock , David Winston
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.
摘要翻译：本发明提供了模拟信号转换。产生电路特性。电路特性被加载到存储器中。模拟电路行为。捕获非前沿电路转换。这发生在软件中。

5. 发明申请

US20060031797A1 Method of timing model abstraction for circuits containing simultaneously switching internal signals 失效
标题翻译：包含同时切换内部信号的电路的定时模型抽象方法
公开(公告)号：US20060031797A1
公开(公告)日：2006-02-09
申请号：US10897349
申请日：2004-07-22
申请人： Jeffrey Soreff , James Warnock
发明人： Jeffrey Soreff , James Warnock
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is for a late arrival, it is determined whether the arrival time for the secondary signal is later than for the first signal. If the test type is for an early arrival, it is determined whether the arrival time for the secondary signal is earlier than for the first signal. If the test type is for the late arrival and the arrival time for the secondary signal is later than for the first signal, assuming maximum interference between the signals. If the test type is for the late arrival and the arrival time for the secondary signal is not later than for the first signal, calculating the actual interference between the signals.
摘要翻译：本发明提供了确定电路中的到达时间。分配主信号的到达时间。分配辅助信号的到达时间。确定测试是提前到达还是稍后到达。如果测试类型是迟到的，则确定辅助信号的到达时间是否晚于第一信号。如果测试类型是用于提前到达，则确定辅助信号的到达时间是否早于第一信号。如果测试类型是迟到的，并且辅助信号的到达时间晚于第一信号，则假定信号之间的最大干扰。如果测试类型为迟到，并且次要信号的到达时间不晚于第一信号，则计算信号之间的实际干扰。

6. 发明申请

US20050071794A1 Methods for modeling latch transparency 有权
标题翻译：锁定透明度建模方法
公开(公告)号：US20050071794A1
公开(公告)日：2005-03-31
申请号：US10962121
申请日：2004-10-08
申请人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。提供了许多其他方面。

7. 发明申请

US20050071790A1 Methods for modeling latch transparency 失效
公开(公告)号：US20050071790A1
公开(公告)日：2005-03-31
申请号：US10672500
申请日：2003-09-26
申请人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.

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