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1. 发明申请

US20070061771A1 METHOD FOR RETICLE SHAPES ANALYSIS AND CORRECTION 失效
标题翻译：用于形式分析和校正的方法
公开(公告)号：US20070061771A1
公开(公告)日：2007-03-15
申请号：US11162586
申请日：2005-09-15
申请人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson , Tad Wilder
发明人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson , Tad Wilder
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
摘要翻译：一种多光栅掩模版设计的掩模版设计校正和电参数提取的方法。该方法包括：选择多小区掩模版设计的小区设计的子集，小区设计子集的每个小区设计具有相应的处理形状，用于确定相应小区设计位置的小区设计子集的每个小区设计的相应形状; 基于每个相应形状的相应单元设计位置，确定每个单元设计的所有对应形状的共同形状处理规则; 以及仅对单元设计的子集的单个单元设计执行相应形状的形状处理，以生成用于所述单元设计的子集的结果数据。还有一种包括计算机可读程序代码的计算机可用介质，其具有适于实现掩模版设计校正和电提取的方法的算法。

2. 发明申请

US20060248488A1 METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION 有权
标题翻译：在过程变化存在下产生匹配延迟的接线方法
公开(公告)号：US20060248488A1
公开(公告)日：2006-11-02
申请号：US10908102
申请日：2005-04-27
申请人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
发明人： Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

3. 发明申请

US20080052656A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 失效
标题翻译：对参数变化的时序分析的灵敏度
公开(公告)号：US20080052656A1
公开(公告)日：2008-02-28
申请号：US11930924
申请日：2007-10-31
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

4. 发明申请

US20060195807A1 METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGATED CIRCUIT 有权
标题翻译：用于在整流电路中评估时序的方法和系统
公开(公告)号：US20060195807A1
公开(公告)日：2006-08-31
申请号：US11383353
申请日：2006-05-15
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

5. 发明申请

US20060101361A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 有权
标题翻译：对参数变化的时序分析的灵敏度
公开(公告)号：US20060101361A1
公开(公告)日：2006-05-11
申请号：US10904309
申请日：2004-11-03
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Jeffrey Oppold , Anthony Polson
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

6. 发明申请

US20050246116A1 METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT 失效
标题翻译：用于评估集成电路中的时序的方法和系统
公开(公告)号：US20050246116A1
公开(公告)日：2005-11-03
申请号：US10709361
申请日：2004-04-29
申请人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
发明人： Eric Foreman , Peter Habitz , David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G01M99/00 , G01R13/00 , G01R31/30
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

7. 发明申请

US20050246117A1 SYSTEM AND METHOD OF ANALYZING TIMING EFFECTS OF SPATIAL DISTRIBUTION IN CIRCUITS 有权
标题翻译：分析电路中空间分布的时序效应的系统与方法
公开(公告)号：US20050246117A1
公开(公告)日：2005-11-03
申请号：US10709362
申请日：2004-04-29
申请人： David Hathaway , Jerry Hayes , Anthony Polson
发明人： David Hathaway , Jerry Hayes , Anthony Polson
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.
摘要翻译：提供了系统和方法，用于通过考虑电路的路径或逻辑锥中的单元或元件的位置来分析电路的定时，包括集成电路。在一个实施例中，可以围绕感兴趣的细胞或元件限定边界区域，并且可以使用边界区域的大小来计算定时松弛变化因子。可以调整边界区域的大小以考虑定时延迟的变化。在其他实施例中，可以使用路径或锥体内的元件或单元的位置或延迟加权位置以及用于计算定时松弛变化因子的质心来计算质心。定时松弛变化因子用于计算电路的路径或逻辑锥的新的定时松弛。

8. 发明申请

US20070050164A1 RING OSCILLATOR STRUCTURE AND METHOD OF SEPARATING RANDOM AND SYSTEMATIC TOLERANCE VALUES 失效
标题翻译：环振荡器结构和分离随机和系统公差值的方法
公开(公告)号：US20070050164A1
公开(公告)日：2007-03-01
申请号：US11162197
申请日：2005-08-31
申请人： Peter Habitz , Jerry Hayes
发明人： Peter Habitz , Jerry Hayes
IPC分类号： G06F19/00
CPC分类号： G05B23/0221 , G01R31/2648
摘要： A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.
摘要翻译：环形振荡器测试结构包括可在不同数量的级之间切换的至少两个重叠环。测量在不同位置形成的一组振荡器中的不同数量的级的延迟分布，其受到不同的系统延迟效应的影响。分析延迟分布，分析系统和随机贡献与分布的标准偏差。

9. 发明申请

US20060243621A1 Corner or edge protector exhibiting improved flexural strength and resistance properties 有权
标题翻译：拐角或边缘保护器具有改善的抗弯强度和抗弯性能
公开(公告)号：US20060243621A1
公开(公告)日：2006-11-02
申请号：US11115355
申请日：2005-04-27
申请人： John Kruelle , Jerry Hayes
发明人： John Kruelle , Jerry Hayes
IPC分类号： B65D85/20
CPC分类号： B65D81/054 , B65D2581/055
摘要： A new and improved external corner protector is fabricated from predetermined materials and comprises a vertex portion, and a pair of leg members which diverge outwardly at a predetermined included angle with respect to each other from the vertex portion. The vertex portion and distal end portions of the leg members have relatively enlarged cross-sectional dimensions relative to the cross-sectional dimensions comprising those portions of the leg members which integrally interconnect the distal end portions of the leg members to the vertex portion, wherein the relatively enlarged cross-sectional dimensions serve to reinforce the vertex portion and to dispose only such relatively enlarged distal end portions of the leg members into contact with the external side wall members of the palletized load which define the external corner region being protected. In this manner, the leg members of the external corner protector are flexed more than has conventionally been the case such that forces are generated and transmitted to the vertex portion so as to rigidify the same whereby the vertex portion will exhibit enhanced flexural strength and bending resistance properties with respect to external forces which may be impressed upon the external corner protector thereby tending to flex or bend the same.
摘要翻译：新的改进的外角保护器由预定材料制成并且包括顶点部分和一对腿部件，其从顶点部分以相对于彼此以预定的夹角向外发散。腿部件的顶点部分和远端部分相对于横截面尺寸具有相对扩大的横截面尺寸，该横截面尺寸包括将腿部件的远端部分与顶点部分整体连接的腿部件的那些部分，其中，相对扩大的横截面尺寸用于加强顶点部分，并且仅将腿部构件的相对扩大的远端部分配置成与限定被保护的外角部区域的托盘化载荷的外侧壁构件接触。以这种方式，外部角部保护器的腿部构件比传统上弯曲得更大，使得力产生并传递到顶点部分以使其刚性化，从而顶部部分将呈现增强的弯曲强度和抗弯曲性相对于可能施加在外部角部保护器上的外力的特性，从而趋于弯曲或弯曲。

10. 发明授权

US08528526B2 Snap assembly decoupled float vapor vent apparatus 有权
标题翻译：捕捉组件去耦浮球蒸气排放装置
公开(公告)号：US08528526B2
公开(公告)日：2013-09-10
申请号：US12630538
申请日：2009-12-03
申请人： Kyle Achor , Jerry Hayes , Michael Richards
发明人： Kyle Achor , Jerry Hayes , Michael Richards
IPC分类号： F02M37/20 , B01D53/00 , B60K15/035 , F16K24/04
CPC分类号： F02M37/20 , F16K31/26 , Y10T137/3099
摘要： This invention relates generally to a vapor vent system for an internal combustion engine such as an outboard marine fuel injected engine. The vapor vent system includes a snap assembly decoupled float vapor vent in order to vent vapors from the vapor separator. The snap assembly design reduces costs, vibration and assembly requirements.
摘要翻译：本发明一般涉及一种用于内燃机的蒸汽排气系统，例如外侧船用燃油喷射发动机。蒸汽排放系统包括一个卡扣组件，去耦浮球蒸汽排气口，以便从蒸气分离器排出蒸气。卡扣组合设计降低了成本，振动和组装要求。

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