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1. 发明授权

US07290148B2 Encryption and decryption communication semiconductor device and recording/reproducing apparatus 失效
标题翻译：加密和解密通信半导体器件和记录/再现装置
公开(公告)号：US07290148B2
公开(公告)日：2007-10-30
申请号：US10352876
申请日：2003-01-29
申请人： Jun Tozawa , Hiroshi Nogami , Tetsuya Shibayama , Tomohiro Kataoka , Hiroshi Fujio
发明人： Jun Tozawa , Hiroshi Nogami , Tetsuya Shibayama , Tomohiro Kataoka , Hiroshi Fujio
IPC分类号： H04L9/00 , H04K1/00
CPC分类号： H04N5/913 , G11B20/00086 , G11B20/0021 , G11B20/00246 , G11B20/00413 , H04N5/765 , H04N5/775 , H04N5/781 , H04N9/8042 , H04N2005/91364
摘要： Disclosed herein is an encryption and decryption communication semiconductor device comprising at least, a communication interface for performing a transfer of data according to a predetermined communication system, one or two or more encryption/decryption circuits which encrypt or decrypt input data in accordance with a predetermined algorithm, and a plurality of external interfaces for performing the input/output of data from and to external devices. The communication interface, the encryption/decryption circuits and the plurality of external interfaces are formed on one semiconductor chip. In the cryption and decryption communication semiconductor device, input data sent from any one of the plurality of external interfaces is encrypted or decrypted by at least one of the encryption/decryption circuits and is capable of being outputted to any different one of the plurality of external interfaces.
摘要翻译：本文公开了一种加密和解密通信半导体装置，至少包括用于根据预定通信系统执行数据传输的通信接口，根据预定的加密/解密电路对输入数据进行加密或解密的一个或两个以上加密/解密电路算法和用于执行从外部设备到外部设备的数据的输入/输出的多个外部接口。通信接口，加密/解密电路和多个外部接口形成在一个半导体芯片上。在加密解密通信半导体装置中，从多个外部接口中的任何一个发送的输入数据由加密/解密电路中的至少一个加密或解密，并能够输出到多个外部接口中的任意一个接口

2. 发明授权

US07107458B2 Authentication communicating semiconductor device 失效
标题翻译：认证通信半导体器件
公开(公告)号：US07107458B2
公开(公告)日：2006-09-12
申请号：US09864304
申请日：2001-05-25
申请人： Toshihisa Oishi , Jun Tozawa , Tetsuya Shibayama , Masato Hamada
发明人： Toshihisa Oishi , Jun Tozawa , Tetsuya Shibayama , Masato Hamada
IPC分类号： H04L9/32
CPC分类号： H04L63/0428 , H04L63/08 , H04L63/14 , H04N5/765 , H04N5/77 , H04N5/775 , H04N5/913 , H04N2005/91364
摘要： In an authentication communicating semiconductor device to enhance protection against illegal copying, a logic analyzer probe or the like is connected to a CPU bus to suppress possibility in which the authentication process is intercepted and is analyzed to break the mechanism of illegal copy protection and the electronic device is modified to set a tampered encryption key to the CPU bus. The authentication communicating semiconductor device includes a semiconductor chip, a main processing unit formed on the chip for generating a key code according to a predetermined algorithm, for determining approval/non-approval of communication of data with an external device, and for controlling the communication; an encryption unit formed on the chip for encrypting and decoding communication data using the key code generated by the main processing unit, and an interface unit formed on the chip for conducting communication with an upper-layer or a lower-layer according to a predetermined protocol.
摘要翻译：在加密认证通信半导体装置中，为了防止非法复制，逻辑分析器探头等连接到CPU总线，以抑制认证过程被拦截的可能性，并被分析以破坏非法拷贝保护的机制和电子设备被修改为将篡改的加密密钥设置到CPU总线。认证通信半导体装置包括半导体芯片，形成在芯片上的主处理单元，用于根据预定算法生成密钥代码，用于确定与外部设备的数据通信的批准/不批准，以及用于控制通信 ; 在芯片上形成的加密单元，用于使用由主处理单元生成的密钥代码对通信数据进行加密和解码;以及接口单元，形成在芯片上，用于根据预定协议进行与上层或下层的通信。

3. 发明申请

US20120294373A1 MOVING IMAGE ENCODING METHOD, MOVING IMAGE DECODING METHOD, MOVING IMAGE ENCODING DEVICE, AND MOVING IMAGE DECODING DEVICE 审中-公开
标题翻译：移动图像编码方法，移动图像解码方法，移动图像编码装置和移动图像解码装置
公开(公告)号：US20120294373A1
公开(公告)日：2012-11-22
申请号：US13519874
申请日：2010-12-14
申请人： Seiji Mochizuki , Kazushi Akie , Tetsuya Shibayama , Kenichi Iwata
发明人： Seiji Mochizuki , Kazushi Akie , Tetsuya Shibayama , Kenichi Iwata
IPC分类号： H04N7/32
CPC分类号： H04N19/85 , H04N19/129 , H04N19/176 , H04N19/423 , H04N19/436
摘要： The moving image encoding method includes encoding macro-blocks included in a landscape picture frame of a moving image having a larger horizontal width in a horizontal direction than a vertical width in a vertical direction by an encoding device. In macro-block encoding, information of the encoded macro-blocks surrounding a macro-block to be encoded is stored in a built-in information storing memory of the encoding device. Further, in the encoding, first a vertical array of macro-blocks at the left end of the horizontal width of the landscape picture frame are encoded sequentially, and the resultant encode information is stored in the information storing memory, and subsequently an adjacent vertical array of the plural macro-blocks located horizontally on the right of the left end of the horizontal width of the landscape picture frame are encoded sequentially.
摘要翻译：运动图像编码方法包括通过编码装置对包括在水平方向上的水平宽度比垂直方向上的垂直宽度的运动图像的景观图像帧中的宏块进行编码。在宏块编码中，将要编码的宏块周围的编码宏块的信息存储在编码装置的内置信息存储存储器中。此外，在编码中，首先对横向图像帧的水平宽度的左端的宏块的垂直阵列进行顺序编码，并将所得到的编码信息存储在信息存储存储器中，随后将相邻的垂直阵列水平位于横向画面帧的水平宽度的左端右侧的多个宏块的顺序编码。

4. 发明授权

US08223838B2 Parallel processing circuit for intra-frame prediction 失效
标题翻译：用于帧内预测的并行处理电路
公开(公告)号：US08223838B2
公开(公告)日：2012-07-17
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04B1/66
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

5. 发明申请

US20080031329A1 DATA PROCESSING CIRCUIT 失效
标题翻译：数据处理电路
公开(公告)号：US20080031329A1
公开(公告)日：2008-02-07
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

6. 发明授权

US08516888B2 Angular velocity sensor and method of manufacturing the same 有权
标题翻译：角速度传感器及其制造方法
公开(公告)号：US08516888B2
公开(公告)日：2013-08-27
申请号：US12491915
申请日：2009-06-25
申请人： Junichi Honda , Teruo Inaguma , Tetsuya Shibayama
发明人： Junichi Honda , Teruo Inaguma , Tetsuya Shibayama
IPC分类号： G01C19/00
CPC分类号： G01C19/5628 , G01C19/5621
摘要： Disclosed is an angular velocity sensor. The angular velocity sensor includes a first layer, a piezoelectric layer, and a second layer. The first layer has a first main surface and a second main surface, and includes a vibrator portion and a base portion that supports the vibrator portion. The piezoelectric layer is formed on the first main surface of the first layer. The second layer is integrally bonded to the base portion on a side of the second main surface of the first layer.
摘要翻译：公开了一种角速度传感器。角速度传感器包括第一层，压电层和第二层。第一层具有第一主表面和第二主表面，并且包括振动器部分和支撑振动器部分的基部。压电层形成在第一层的第一主表面上。第二层在第一层的第二主表面的一侧整体地结合到基部。

7. 发明申请

US20070294514A1 Picture Processing Engine and Picture Processing System 审中-公开
标题翻译：图片处理引擎和图片处理系统
公开(公告)号：US20070294514A1
公开(公告)日：2007-12-20
申请号：US11688894
申请日：2007-03-21
申请人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
发明人： Koji Hosogi , Masakazu Ehama , Hiroaki Nakata , Kenichi Iwata , Seiji Mochizuki , Takafumi Yuasa , Yukifumi Kobayashi , Tetsuya Shibayama , Hiroshi Ueda , Masaki Nobori
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： To provide a technique to reduce power consumption when carrying out image processing by processors. For the purpose of this, for example, a means for specifying a two-dimensional source register and destination register is provided in an operand of an instruction, and the processor includes a means which executes calculation using a plurality of source registers in a plurality of cycles and obtains a plurality of destinations. Moreover, in an instruction to obtain a destination using a plurality of source registers and consuming a plurality of cycles, a data rounding processing part is connected to a final stage of a pipeline. With such configurations, the power consumed when reading an instruction memory is reduced by reducing the access frequency to the instruction memory, for example.
摘要翻译：提供一种在进行处理器进行图像处理时降低功耗的技术。为此目的，例如，在指令的操作数中提供用于指定二维源寄存器和目标寄存器的装置，并且处理器包括使用多个源寄存器中的多个源寄存器执行计算的装置循环并获得多个目的地。此外，在使用多个源寄存器获取目的地并消耗多个周期的指令中，数据舍入处理部分连接到流水线的最后一级。通过这样的配置，例如通过减少对指令存储器的访问频率来减少读取指令存储器时消耗的功率。

8. 发明申请

US20060239349A1 Image coding unit and image coding method 审中-公开
标题翻译：图像编码单元和图像编码方法
公开(公告)号：US20060239349A1
公开(公告)日：2006-10-26
申请号：US11406389
申请日：2006-04-19
申请人： Tetsuya Shibayama
发明人： Tetsuya Shibayama
IPC分类号： H04N7/12
CPC分类号： H04N19/11 , H04N19/176 , H04N19/61
摘要： An image coding unit and an image coding method which assure high speed and high image quality with a simple structure. For coding plural sub macroblocks into which a macroblock to be coded is divided, plural types of virtual predicted image data are generated using target image data to be coded in a sub macroblock concerned and an adjacent sub macroblock, and intra-frame prediction mode decision information to select the most suitable virtual predicted image data of one type from among the plural types of virtual predicted image data is generated. According to this prediction mode decision information, real predicted image data is generated by intra-frame prediction operation using reference image data in the adjacent sub macroblock, and difference from the target image data is coded.
摘要翻译：一种图像编码单元和图像编码方法，其以简单的结构确保高速和高图像质量。为了编码要分割的要编码的宏块的多个子宏块，使用要在有关的子宏块和相邻子宏块中编码的目标图像数据来生成多种类型的虚拟预测图像数据，以及帧内预测模式决定信息从多个类型的虚拟预测图像数据中选择一种类型的最合适的虚拟预测图像数据。根据该预测模式判定信息，通过使用相邻子宏块中的参考图像数据的帧内预测运算来生成实际预测图像数据，并且对来自目标图像数据的差异进行编码。

9. 发明申请

US20120263233A1 DATA PROCESSING CIRCUIT 审中-公开
标题翻译：数据处理电路
公开(公告)号：US20120263233A1
公开(公告)日：2012-10-18
申请号：US13533570
申请日：2012-06-26
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

10. 发明申请

US20100000322A1 ANGULAR VELOCITY SENSOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：角速度传感器及其制造方法
公开(公告)号：US20100000322A1
公开(公告)日：2010-01-07
申请号：US12491915
申请日：2009-06-25
申请人： Junichi Honda , Teruo Inaguma , Tetsuya Shibayama
发明人： Junichi Honda , Teruo Inaguma , Tetsuya Shibayama
IPC分类号： G01C19/56 , H05K3/36
CPC分类号： G01C19/5628 , G01C19/5621
摘要： Disclosed is an angular velocity sensor. The angular velocity sensor includes a first layer, a piezoelectric layer, and a second layer. The first layer has a first main surface and a second main surface, and includes a vibrator portion and a base portion that supports the vibrator portion. The piezoelectric layer is formed on the first main surface of the first layer. The second layer is integrally bonded to the base portion on a side of the second main surface of the first layer.
摘要翻译：公开了一种角速度传感器。角速度传感器包括第一层，压电层和第二层。第一层具有第一主表面和第二主表面，并且包括振动器部分和支撑振动器部分的基部。压电层形成在第一层的第一主表面上。第二层在第一层的第二主表面的一侧整体地结合到基部。

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