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1. 发明申请

US20080099821A1 FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：闪存存储器件及其制造方法
公开(公告)号：US20080099821A1
公开(公告)日：2008-05-01
申请号：US11618675
申请日：2006-12-29
申请人： Jum Soo Kim , Seok Kiu Lee
发明人： Jum Soo Kim , Seok Kiu Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method of manufacturing semiconductor devices includes providing a semiconductor substrate including first active areas and isolation areas alternately arranged to be parallel to each other and second active areas connecting the first active areas to each other. A tunnel insulating layer, a charge storage layer, and an isolation mask are formed on the semiconductor substrate. The isolation mask, the charge storage layer, the tunnel insulating layer, and the semiconductor substrate are etched to form a trench on the isolation area. An isolation structure is formed on the trench. A dielectric layer, a conductive layer for a control gate, and a hard mask are sequentially formed on a structure that includes the isolation structure. The hard mask, the conductive layer for the control gate, the dielectric layer, and the charge storage layer are patterned to form drain select lines, word lines and source select lines intersecting the first active area. Junction areas are formed on the first active areas through an ion implanting process. A common source is formed on the first active areas and the second active area between adjacent source select lines.
摘要翻译：一种制造半导体器件的方法包括提供半导体衬底，该半导体衬底包括交替布置为彼此平行的第一有源区和隔离区以及将第一有源区彼此连接的第二有源区。隧道绝缘层，电荷存储层和隔离掩模形成在半导体衬底上。蚀刻隔离掩模，电荷存储层，隧道绝缘层和半导体衬底，以在隔离区域上形成沟槽。隔离结构形成在沟槽上。介电层，用于控制栅极的导电层和硬掩模依次形成在包括隔离结构的结构上。将硬掩模，用于控制栅极的导电层，电介质层和电荷存储层图案化以形成与第一有源区相交的漏极选择线，字线和源选择线。通过离子注入工艺在第一有源区上形成接合区域。在相邻的源选择线之间的第一有源区和第二有源区上形成公共源。

2. 发明申请

US20080003750A1 METHOD OF MANUFACTURING FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20080003750A1
公开(公告)日：2008-01-03
申请号：US11609886
申请日：2006-12-12
申请人： Jum Soo Kim , Hee Hyun Chang
发明人： Jum Soo Kim , Hee Hyun Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of manufacturing a non-volatile memory device includes providing a floating gate layer over a semiconductor substrate. The floating gate layer and the semiconductor substrate are etched to form a trench. An isolation structure is formed in the trench. An upper portion of the isolation structure is etched, wherein an upper sidewall of the floating gate layer is exposed by the etching of the upper portion of the isolation structure. An oxide layer is formed on the floating gate layer to round an upper corner of the floating gate layer. A control gate layer is formed over the floating gate layer.
摘要翻译：制造非易失性存储器件的方法包括在半导体衬底上提供浮动栅层。蚀刻浮栅和半导体衬底以形成沟槽。在沟槽中形成隔离结构。蚀刻隔离结构的上部，其中通过对隔离结构的上部的蚀刻来暴露浮栅的上侧壁。在浮置栅极层上形成氧化物层以围绕浮动栅极层的上角。在浮栅层上形成控制栅极层。

3. 发明授权

US07074682B2 Method for fabricating a semiconductor device having self aligned source (SAS) crossing trench 失效
标题翻译：用于制造具有自对准源（SAS）交叉沟槽的半导体器件的方法
公开(公告)号：US07074682B2
公开(公告)日：2006-07-11
申请号：US10951503
申请日：2004-09-27
申请人： Jum Soo Kim , Sung Mun Jung
发明人： Jum Soo Kim , Sung Mun Jung
IPC分类号： H01L21/71
CPC分类号： H01L27/11521 , H01L27/115
摘要： In order to provide a method for preventing the channel length from being shortened as well as reducing the SAS resistance, the semiconductor device according to the present invention is manufactured by forming continuous linear trench lines on a semiconductor substrate, forming gate oxide lines on the semiconductor substrate between the trench lines, forming gate lines on the trench lines and the gate oxide lines, the gate lines being substantially perpendicular to the trench lines, etching the gate oxide lines and trench lines positioned between the gate lines, to form an etched region forming self aligned sources (SASs) by implanting impurity ions into the etched region, forming spacers on sidewalls of the gate lines, and implanting impurity ions in the SAS region using the spacers as a mask.
摘要翻译：为了提供防止通道长度缩短以及降低SAS电阻的方法，根据本发明的半导体器件通过在半导体衬底上形成连续的线性沟槽线，在半导体衬底上形成栅极氧化物线沟槽线之间的衬底，在沟槽线上形成栅极线和栅极氧化物线，栅极线基本上垂直于沟槽线，蚀刻位于栅极线之间的栅极氧化物线和沟槽线，以形成蚀刻区域通过将杂质离子注入到蚀刻区域中形成自对准源（SAS），在栅极线的侧壁上形成间隔物，并且使用间隔物作为掩模将杂质离子注入到SAS区域中。

4. 发明授权

US07439603B2 Non-volatile memory device and fabricating method thereof 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07439603B2
公开(公告)日：2008-10-21
申请号：US11701484
申请日：2007-02-02
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L23/58
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.
摘要翻译：本发明提供了一种非易失性存储器件及其制造方法，通过该非易失性存储器件可以降低电池尺寸，尽管电池集成度高，并且器件制造方便。本发明包括布置在半导体衬底的器件隔离区域中的至少两个沟槽隔离层，每个具有第一深度，第一导电类型阱布置在所述至少两个沟槽隔离层之间，以具有小于第一深度的第二深度第二导电型源极区域和第二导电型漏极区域，布置在第一导电类型阱的规定的上部中，通过其间的沟道区域彼此分离，在该沟道区域上的ONO层半导体衬底，ONO层包括低氧化物层，氮化物层和上部氧化物层，以及ONO层上的字线导体层。

5. 发明授权

US07253056B2 Flash memory cell and method for manufacturing the same 有权
公开(公告)号：US07253056B2
公开(公告)日：2007-08-07
申请号：US11315148
申请日：2005-12-23
申请人： Jum Soo Kim , Ji Hyung Yune
发明人： Jum Soo Kim , Ji Hyung Yune
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer are patterned to form a plurality of gate lines. Deep ion implantation in a deep portion of the active region is performed using a self-aligned source mask. The active region and the trench region are exposed through the self-aligned source mask by etching the isolation layer between the plurality of gate lines using the self-aligned source mask to form a common source region. Ions are implanted in the common source region using the self-aligned source mask.

6. 发明授权

US07183155B2 Non-volatile memory device and fabricating method thereof 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07183155B2
公开(公告)日：2007-02-27
申请号：US11019299
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.
摘要翻译：本发明提供了一种非易失性存储器件及其制造方法，通过该非易失性存储器件可以降低电池尺寸，尽管电池集成度高，并且器件制造方便。本发明包括布置在半导体衬底的器件隔离区域中的至少两个沟槽隔离层，每个具有第一深度，第一导电类型阱布置在所述至少两个沟槽隔离层之间，以具有小于第一深度的第二深度第二导电型源极区域和第二导电型漏极区域，布置在第一导电类型阱的规定的上部中，通过其间的沟道区域彼此分离，在该沟道区域上的ONO层半导体衬底，ONO层包括低氧化物层，氮化物层和上部氧化物层，以及ONO层上的字线导体层。

7. 发明申请

US20070034929A1 FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：闪存存储器件及其制造方法
公开(公告)号：US20070034929A1
公开(公告)日：2007-02-15
申请号：US11164605
申请日：2005-11-30
申请人： Joo Hwang , Jum Soo Kim
发明人： Joo Hwang , Jum Soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A flash memory device and method of manufacturing the same includes a string structure having source select lines, a number of word lines and drain select lines, a first insulating film is filled between the word lines, between the word lines and the source select lines and between the word lines and the drain select lines upon formation of a self-aligned contact. A spacer is formed using a second insulating film on sidewalls of the source select lines and the drain select lines. In this case, the first insulating film has a dielectric constant value lower than that of the second insulating film. Accordingly, a stabilized self-aligned contact can be formed, a Vt disturbance phenomenon in a program operation can be minimized, and the operation speed of the device can be improved.
摘要翻译：闪存器件及其制造方法包括具有源极选择线，多个字线和漏极选择线的串联结构，在字线之间，字线和源选择线之间填充第一绝缘膜，以及在形成自对准接触之间的字线和漏极选择线之间。在源极选择线和漏极选择线的侧壁上使用第二绝缘膜形成间隔物。在这种情况下，第一绝缘膜的介电常数值低于第二绝缘膜。因此，可以形成稳定的自对准接触，能够使编程动作中的Vt干扰现象最小化，能够提高装置的动作速度。

8. 发明授权

US07169670B2 Method of forming gate oxide layer in semiconductor device 失效
标题翻译：在半导体器件中形成栅氧化层的方法
公开(公告)号：US07169670B2
公开(公告)日：2007-01-30
申请号：US10880691
申请日：2004-06-30
申请人： Min Kyu Lee , Hee Hyun Chang , Jum Soo Kim , Jung Ryul Ahn
发明人： Min Kyu Lee , Hee Hyun Chang , Jum Soo Kim , Jung Ryul Ahn
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/105 , H01L27/11534 , Y10S438/981
摘要： Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and the surface of the semiconductor substrate of the low voltage region.
摘要翻译：提供一种形成半导体器件的方法，包括以下步骤：提供具有低电压区域和高电压区域的半导体衬底; 在半导体衬底上依次形成焊盘氧化物层和焊盘氮化物层; 去除高电压区域的半导体衬底上的衬垫氮化物层和衬垫氧化物层，其中高压区域的半导体衬底的表面被暴露和凹陷; 在高电压区域的半导体衬底的表面上形成牺牲氧化物层; 去除牺牲层; 在所述高电压区域的半导体衬底的表面上形成第一栅氧化层; 去除低电压区域的半导体衬底上留下的衬垫氧化物层和衬垫氮化物层，其中低电压区域的半导体衬底的表面露出并凹陷; 以及在所述第一栅极氧化物层和所述低电压区域的所述半导体衬底的表面上形成第二栅极氧化物层。

9. 发明授权

US08520440B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08520440B2
公开(公告)日：2013-08-27
申请号：US13297467
申请日：2011-11-16
申请人： Jung Ryul Ahn , Sang Hyun Oh , Jum Soo Kim
发明人： Jung Ryul Ahn , Sang Hyun Oh , Jum Soo Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11524
摘要： A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor; connecting electrically the first memory cell group to the second memory cell group during a program operation or a read operation of the first memory cell group or the second memory cell group; and performing separately an erase operation of the first memory cell group and an erase operation of the second memory cell group, selecting simultaneously one of the first dummy element and the second dummy element during the erase operation of the selected memory cell group.
摘要翻译：一种操作半导体存储器件的方法包括具有存储单元串的存储器阵列，存储单元串包括具有存储单元的第一和第二存储单元组，第一和第二虚设元件，漏极选择晶体管和源选择晶体管，其中第一存储单元组和第二存储单元组布置在漏极选择晶体管和源极选择晶体管之间; 在第一存储单元组或第二存储单元组的编程操作或读操作期间将第一存储单元组电连接到第二存储单元组; 以及分别执行第一存储单元组的擦除操作和第二存储单元组的擦除操作，在所选存储单元组的擦除操作期间同时选择第一虚拟元件和第二虚设元件中的一个。

10. 发明授权

US07259074B2 Trench isolation method in flash memory device 有权
标题翻译：闪存设备中的沟槽隔离方法
公开(公告)号：US07259074B2
公开(公告)日：2007-08-21
申请号：US11019302
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invention includes forming a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon, forming a trench in the semiconductor substrate corresponding to the device isolation area, removing an exposed portion of the first insulating layer pattern enough to expose a portion of the semiconductor substrate in the active area adjacent to the trench, forming a sidewall oxide layer on an inside of the trench and the exposed portion of the semiconductor substrate, filling up the trench with a third insulating layer to cover the sidewall oxide layer, and removing the mask layer pattern.
摘要翻译：本发明提供了一种闪速存储器件中的沟槽隔离方法，通过这种方法，在沟槽隔离层的边缘附近形成厚的衬垫氧化物层，增强了器件的稳定性和可靠性。本发明包括在半导体衬底上形成掩模层图案以暴露器件隔离区域而覆盖其有效区域，掩模层图案包括第一绝缘层图案和叠置在其上的第二绝缘层图案，形成沟槽所述半导体衬底对应于所述器件隔离区域，去除所述第一绝缘层图案的暴露部分以足以暴露所述半导体衬底在与所述沟槽相邻的有源区域中的一部分，在所述沟槽的内部形成侧壁氧化物层，以及半导体衬底的暴露部分，用第三绝缘层填充沟槽以覆盖侧壁氧化物层，以及去除掩模层图案。

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