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1. 发明授权

US07439603B2 Non-volatile memory device and fabricating method thereof 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07439603B2
公开(公告)日：2008-10-21
申请号：US11701484
申请日：2007-02-02
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L23/58
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.
摘要翻译：本发明提供了一种非易失性存储器件及其制造方法，通过该非易失性存储器件可以降低电池尺寸，尽管电池集成度高，并且器件制造方便。本发明包括布置在半导体衬底的器件隔离区域中的至少两个沟槽隔离层，每个具有第一深度，第一导电类型阱布置在所述至少两个沟槽隔离层之间，以具有小于第一深度的第二深度第二导电型源极区域和第二导电型漏极区域，布置在第一导电类型阱的规定的上部中，通过其间的沟道区域彼此分离，在该沟道区域上的ONO层半导体衬底，ONO层包括低氧化物层，氮化物层和上部氧化物层，以及ONO层上的字线导体层。

2. 发明授权

US07183155B2 Non-volatile memory device and fabricating method thereof 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07183155B2
公开(公告)日：2007-02-27
申请号：US11019299
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.
摘要翻译：本发明提供了一种非易失性存储器件及其制造方法，通过该非易失性存储器件可以降低电池尺寸，尽管电池集成度高，并且器件制造方便。本发明包括布置在半导体衬底的器件隔离区域中的至少两个沟槽隔离层，每个具有第一深度，第一导电类型阱布置在所述至少两个沟槽隔离层之间，以具有小于第一深度的第二深度第二导电型源极区域和第二导电型漏极区域，布置在第一导电类型阱的规定的上部中，通过其间的沟道区域彼此分离，在该沟道区域上的ONO层半导体衬底，ONO层包括低氧化物层，氮化物层和上部氧化物层，以及ONO层上的字线导体层。

3. 发明授权

US07259074B2 Trench isolation method in flash memory device 有权
标题翻译：闪存设备中的沟槽隔离方法
公开(公告)号：US07259074B2
公开(公告)日：2007-08-21
申请号：US11019302
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invention includes forming a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon, forming a trench in the semiconductor substrate corresponding to the device isolation area, removing an exposed portion of the first insulating layer pattern enough to expose a portion of the semiconductor substrate in the active area adjacent to the trench, forming a sidewall oxide layer on an inside of the trench and the exposed portion of the semiconductor substrate, filling up the trench with a third insulating layer to cover the sidewall oxide layer, and removing the mask layer pattern.
摘要翻译：本发明提供了一种闪速存储器件中的沟槽隔离方法，通过这种方法，在沟槽隔离层的边缘附近形成厚的衬垫氧化物层，增强了器件的稳定性和可靠性。本发明包括在半导体衬底上形成掩模层图案以暴露器件隔离区域而覆盖其有效区域，掩模层图案包括第一绝缘层图案和叠置在其上的第二绝缘层图案，形成沟槽所述半导体衬底对应于所述器件隔离区域，去除所述第一绝缘层图案的暴露部分以足以暴露所述半导体衬底在与所述沟槽相邻的有源区域中的一部分，在所述沟槽的内部形成侧壁氧化物层，以及半导体衬底的暴露部分，用第三绝缘层填充沟槽以覆盖侧壁氧化物层，以及去除掩模层图案。

4. 发明授权

US07214581B2 Method of fabricating flash memory device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US07214581B2
公开(公告)日：2007-05-08
申请号：US11019300
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a method of fabricating a flash memory device, in which floating gates in neighbor cells are separated from each other without using photolithography, which enhances electrical characteristics of the device, and which facilitates a cell size reduction. The present invention includes forming a mask defining a trench forming area on a semiconductor substrate, forming a trench in the semiconductor layer by removing a portion of the semiconductor layer using the mask, forming a device isolation layer filling up the trench to maintain an effective isolation layer thickness exceeding a predefined thickness, removing the mask, forming a conductor layer over the substrate including the device isolation layer, planarizing the conductor layer and the device isolation layer to lie in a same plane, and forming an insulating layer over the substrate including the conductor patterns.
摘要翻译：本发明提供一种制造闪存器件的方法，其中相邻单元中的浮置栅极彼此分离而不使用光刻，这增强了器件的电气特性，并且有助于电池尺寸减小。本发明包括在半导体衬底上形成限定沟槽形成区域的掩模，通过使用掩模去除半导体层的一部分，在半导体层中形成沟槽，形成填充沟槽的器件隔离层以保持有效隔离层厚度超过预定厚度，去除掩模，在包括器件隔离层的衬底上形成导体层，将导体层和器件隔离层平坦化在同一平面上，并在衬底上形成绝缘层，包括导体图案。

5. 发明授权

US07074682B2 Method for fabricating a semiconductor device having self aligned source (SAS) crossing trench 失效
标题翻译：用于制造具有自对准源（SAS）交叉沟槽的半导体器件的方法
公开(公告)号：US07074682B2
公开(公告)日：2006-07-11
申请号：US10951503
申请日：2004-09-27
申请人： Jum Soo Kim , Sung Mun Jung
发明人： Jum Soo Kim , Sung Mun Jung
IPC分类号： H01L21/71
CPC分类号： H01L27/11521 , H01L27/115
摘要： In order to provide a method for preventing the channel length from being shortened as well as reducing the SAS resistance, the semiconductor device according to the present invention is manufactured by forming continuous linear trench lines on a semiconductor substrate, forming gate oxide lines on the semiconductor substrate between the trench lines, forming gate lines on the trench lines and the gate oxide lines, the gate lines being substantially perpendicular to the trench lines, etching the gate oxide lines and trench lines positioned between the gate lines, to form an etched region forming self aligned sources (SASs) by implanting impurity ions into the etched region, forming spacers on sidewalls of the gate lines, and implanting impurity ions in the SAS region using the spacers as a mask.
摘要翻译：为了提供防止通道长度缩短以及降低SAS电阻的方法，根据本发明的半导体器件通过在半导体衬底上形成连续的线性沟槽线，在半导体衬底上形成栅极氧化物线沟槽线之间的衬底，在沟槽线上形成栅极线和栅极氧化物线，栅极线基本上垂直于沟槽线，蚀刻位于栅极线之间的栅极氧化物线和沟槽线，以形成蚀刻区域通过将杂质离子注入到蚀刻区域中形成自对准源（SAS），在栅极线的侧壁上形成间隔物，并且使用间隔物作为掩模将杂质离子注入到SAS区域中。

6. 发明授权

US07297595B2 Non-volatile memory device and fabricating method thereof 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07297595B2
公开(公告)日：2007-11-20
申请号：US11019304
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/7883
摘要： The present invention provides a non-volatile memory device and fabricating method thereof, in which a height of a floating gate conductor layer pattern is sustained without lowering a degree of integration and by which a coupling ratio is raised. The present invention includes a trench type device isolation layer defining an active area within a semiconductor substrate, a recess in an upper part of the device isolation layer to have a prescribed depth, a tunnel oxide layer on the active area of the semiconductor substrate, a floating gate conductor layer pattern on the tunnel oxide layer, a conductive floating spacer layer provided to a sidewall of the floating gate conductor layer pattern and a sidewall of the recess, a gate-to-gate insulating layer on the floating fate conductor layer pattern and the conductive floating spacer layer, and a control gate conductor layer on the gate-to-gate insulating layer.
摘要翻译：本发明提供了一种非易失性存储器件及其制造方法，其中浮动栅极导体层图案的高度在不降低积分度的情况下被维持并且耦合比率被提高。本发明包括限定半导体衬底内的有源区域的沟槽型器件隔离层，在器件隔离层的上部具有规定深度的凹部，半导体衬底的有源区上的隧道氧化物层，在所述隧道氧化物层上的浮栅导体层图案，设置在所述浮栅导体层图案的侧壁和所述凹部的侧壁的导电浮动间隔层，所述浮置导体层图案上的栅极至栅极绝缘层，以及导电浮动间隔层，以及栅极至栅极绝缘层上的控制栅极导体层。

7. 发明授权

US07122428B2 Device isolation method of semiconductor memory device and flash memory device fabricating method using the same 有权
标题翻译：半导体存储器件的器件隔离方法及其使用的闪存器件制造方法
公开(公告)号：US07122428B2
公开(公告)日：2006-10-17
申请号：US11019352
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a device isolation method of a semiconductor memory device and flash memory device fabricating method using the same, which can prevent a bridge occurrence between cells. The present invention includes forming a nitride layer pattern defining a trench forming area on a semiconductor substrate, forming a spacer on a sidewall of the nitride layer pattern, forming a trench in the semiconductor layer by removing a portion of the semiconductor layer using the nitride layer pattern and the spacer as an etch mask, forming a device isolation layer filling up the trench, removing the nitride layer pattern and the spacer to complete the device isolation layer, forming a conductor layer over the substrate including the device isolation layer, planarizing the conductor layer and the device isolation layer to lie in a same plane, and forming an insulating layer over the substrate.
摘要翻译：本发明提供了一种半导体存储器件的器件隔离方法和使用该半导体存储器件的闪存器件制造方法，其可以防止单元之间的桥接发生。本发明包括在半导体衬底上形成限定沟槽形成区域的氮化物层图案，在氮化物层图案的侧壁上形成间隔物，通过使用氮化物层去除半导体层的一部分，在半导体层中形成沟槽形成作为蚀刻掩模的间隔物，形成填充沟槽的器件隔离层，去除氮化物层图案和间隔物以完成器件隔离层，在包括器件隔离层的衬底上形成导体层，平坦化导体层和器件隔离层位于同一平面上，并在衬底上形成绝缘层。

8. 发明授权

US07122427B2 Method of fabricating non-volatile memory device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07122427B2
公开(公告)日：2006-10-17
申请号：US11019301
申请日：2004-12-23
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a method of fabricating a non-volatile memory device, in which trench isolation can be achieved using an insulating layer that needs no separate removal process. The present invention includes sequentially forming a first insulating layer, a first conductor layer, and a second insulating layer on a semiconductor substrate, patterning the second insulating layer, the first conductor layer, and the first insulating layer to expose a prescribed portion of the semiconductor substrate, forming a trench having a prescribed depth in the semiconductor substrate by removing the exposed portion of the semiconductor substrate, forming a third insulating layer on the second insulating layer including the trench, planarizing the third insulating layer to remove the second insulating layer until the first conductor layer is exposed, forming a fourth insulating layer on the exposed first conductor layer and the remaining third insulating layer, and forming a second conductor layer on the fourth insulating layer.
摘要翻译：本发明提供一种制造非易失性存储器件的方法，其中可以使用不需要单独去除工艺的绝缘层来实现沟槽隔离。本发明包括在半导体衬底上依次形成第一绝缘层，第一导体层和第二绝缘层，图案化第二绝缘层，第一导体层和第一绝缘层以暴露半导体的规定部分衬底，通过去除半导体衬底的暴露部分在半导体衬底中形成具有规定深度的沟槽，在包括沟槽的第二绝缘层上形成第三绝缘层，平坦化第三绝缘层以移除第二绝缘层，直到暴露第一导体层，在暴露的第一导体层和剩余的第三绝缘层上形成第四绝缘层，并在第四绝缘层上形成第二导体层。

9. 发明授权

US06844231B2 Method of manufacturing a flash memory cell using a self-aligned floating gate 失效
标题翻译：使用自对准浮动栅极制造闪速存储器单元的方法
公开(公告)号：US06844231B2
公开(公告)日：2005-01-18
申请号：US10310746
申请日：2002-12-05
申请人： Jum Soo Kim , Sung Mun Jung , Jung Ryul Ahn , Young Ki Shin , Young Bok Lee
发明人： Jum Soo Kim , Sung Mun Jung , Jung Ryul Ahn , Young Ki Shin , Young Bok Lee
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/76235
摘要： A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.
摘要翻译：一种制造闪存单元的方法。该方法包括控制在形成用于埋入沟槽的沟槽绝缘膜的工艺之前/之后执行的沟槽绝缘膜的壁牺牲氧化过程，壁氧化过程和清洁过程，以将沟槽绝缘膜蚀刻到期望的空间。因此，可以最大限度地确保浮动栅极的耦合比，并且实现更小尺寸的器件。

10. 发明授权

US06721208B2 Method of erasing flash memory cells 有权
标题翻译：擦除闪存单元的方法
公开(公告)号：US06721208B2
公开(公告)日：2004-04-13
申请号：US10315246
申请日：2002-12-10
申请人： Sung Mun Jung , Jum Soo Kim
发明人： Sung Mun Jung , Jum Soo Kim
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/16
摘要： The present invention relates to a method of erasing flash memory cells. In the flash memory cell having a substrate, a source, a drain, a tunnel oxide film, a floating gate, a dielectric film and a control gate, the method of erasing the flash memory cell comprises the steps of performing an erase operation for the cell, by applying a negative voltage being an erase voltage to the control gate and a positive voltage being an erase voltage to the substrate, discharging the control gate by making the control gate grounded, discharging the source by making the source grounded, and simultaneously performing a discharge operation and a recovery operation by making the substrate grounded. Therefore, the threshold voltages of the cells can be converted to have a constant voltage even though additional recovery operation is not performed.
摘要翻译：本发明涉及擦除闪存单元的方法。在具有衬底，源极，漏极，隧道氧化物膜，浮动栅极，电介质膜和控制栅极的闪速存储器单元中，擦除闪速存储器单元的方法包括以下步骤：通过向控制栅极施加作为擦除电压的负电压和向基板施加作为擦除电压的正电压，通过使控制栅极接地来对控制栅极进行放电，通过使源极接地来放电源，同时执行通过使基板接地来进行放电动作和恢复动作。因此，即使不执行附加的恢复操作，也可以将单元的阈值电压转换为恒定的电压。

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