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1. 发明申请

US20050032491A1 Method and apparatus for measuring communications link quality 失效
标题翻译：测量通信链路质量的方法和装置
公开(公告)号：US20050032491A1
公开(公告)日：2005-02-10
申请号：US10636992
申请日：2003-08-07
申请人： Juan-Antonio Carballo , Jeffrey Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey Burns , Ivan Vo
IPC分类号： H04B17/00 , H04B17/02
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

2. 发明申请

US20060223478A1 METHOD AND APPARATUS FOR MEASURING COMMUNICATIONS LINK QUALITY 失效
标题翻译：用于测量通信链路质量的方法和装置
公开(公告)号：US20060223478A1
公开(公告)日：2006-10-05
申请号：US11424209
申请日：2006-06-14
申请人： Juan-Antonio Carballo , Jeffrey Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey Burns , Ivan Vo
IPC分类号： H04B1/00 , H04B1/10 , H04B15/00
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

3. 发明授权

US06621358B2 Differential voltage controlled oscillator, and method therefor 失效
标题翻译：差分压控振荡器及其方法
公开(公告)号：US06621358B2
公开(公告)日：2003-09-16
申请号：US10015384
申请日：2001-12-17
申请人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Ivan Vo
IPC分类号： H03B500
CPC分类号： H03K5/133 , H03K3/0322 , H03K2005/00208 , H03K2005/00234
摘要： In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.
摘要翻译：在第一形式中，压控振荡器包括以环形连接的延迟单元，以及连接到选择性地旁路各组延迟单元的控制元件。延迟单元可操作以接收相应的差分输入并产生反相输出。控制元件可操作以接收相应的差分输入并产生具有可变延迟的非反相输出。响应于各个差分控制电压，控制元件延迟是可变的。

4. 发明授权

US07636556B2 Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices 有权
标题翻译：数字传输电路和方法通过多个加权驱动器片提供可选择的功耗
公开(公告)号：US07636556B2
公开(公告)日：2009-12-22
申请号：US12015458
申请日：2008-01-16
申请人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译：通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。

5. 发明授权

US07353007B2 Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices 有权
标题翻译：数字传输电路和方法通过多个加权驱动片提供可选择的功耗
公开(公告)号：US07353007B2
公开(公告)日：2008-04-01
申请号：US11050019
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译：通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低了发射机功耗，面积和复杂度。级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。

6. 发明授权

US06801025B2 Method and apparatus for control of voltage regulation 失效
公开(公告)号：US06801025B2
公开(公告)日：2004-10-05
申请号：US10289815
申请日：2002-11-07
申请人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo
发明人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo
IPC分类号： G05F110
CPC分类号： H02M3/073 , G06F1/26 , G11C5/145
摘要： According to an apparatus form of the invention, integrated circuitry on a single chip includes a bit-programmable voltage regulator supplying voltage to first circuitry on the chip. The integrated circuitry also includes second circuitry operable for characterizing performance of the first circuitry. Control circuitry on the chip is operable, responsive to the characterizing performed by the second circuitry, to output at least one digital control bit for controlling the regulator output voltage supplying the first circuitry. In another aspect, the integrated circuitry is operable to receive an externally generated, time-based reference signal, and the second circuitry includes an on-chip oscillator for generating a performance characterizing signal. The performance characterizing signal varies in frequency in correspondence with the performance of the first circuitry. The control circuitry receives the reference signal and the performance characterizing signal and responsively generates the at least one control bit.

7. 发明授权

US07269397B2 Method and apparatus for measuring communications link quality 失效
标题翻译：测量通信链路质量的方法和装置
公开(公告)号：US07269397B2
公开(公告)日：2007-09-11
申请号：US11424209
申请日：2006-06-14
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
IPC分类号： H04B17/02
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

8. 发明申请

US20060171477A1 Digital transmission circuit and method providing selectable power consumption via single-ended or differential operation 有权
公开(公告)号：US20060171477A1
公开(公告)日：2006-08-03
申请号：US11050605
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04L25/00
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.

9. 发明授权

US08010066B2 Digital transmission circuit and interface providing selectable power consumption via multiple weighted driver slices 有权
标题翻译：数字传输电路和接口通过多个加权驱动器片提供可选择的功耗
公开(公告)号：US08010066B2
公开(公告)日：2011-08-30
申请号：US12024448
申请日：2008-02-01
申请人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译：数字传输电路和接口通过多个加权驱动器片提供可选择的功耗，提高接口的灵活性，同时在可能的同时降低发射机功耗，面积和复杂性。级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。

10. 发明授权

US07522670B2 Digital transmission circuit and method providing selectable power consumption via single-ended or differential operation 有权
标题翻译：数字传输电路和方法通过单端或差分操作提供可选择的功耗
公开(公告)号：US07522670B2
公开(公告)日：2009-04-21
申请号：US11050605
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04B3/00
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.
摘要翻译：通过单端或差分操作提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。通过发射机输出驱动器级提供差分路径，并且当传输电路处于低功率操作模式时，部分被选择性地禁用。单端到差分转换器电路可用于构建差分信号以输出到最终的驱动级。可以通过来自信道质量测量单元的反馈来进行功率模式的选择，或者可以在编程控制下进行硬连线或选择。当条件允许使用低功率单端模式时，较低功率单端模式的较长延迟或偏斜由信道的放宽要求进行补偿。

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