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1. 发明申请

US20070004129A1 SEMICONDUCTOR DEVICE HAVING FINFET AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有FINFET的半导体器件及其制造方法
公开(公告)号：US20070004129A1
公开(公告)日：2007-01-04
申请号：US11427734
申请日：2006-06-29
申请人： Ju-Yong LEE , Tae-Young CHUNG , Kyu-Hyun LEE , Yong-Sung KIM
发明人： Ju-Yong LEE , Tae-Young CHUNG , Kyu-Hyun LEE , Yong-Sung KIM
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： In one embodiment, a semiconductor device includes a plurality of fin-shaped active regions defined by a trench formed in a substrate with a predetermined depth; an isolation layer formed inside the trench and comprising a first insulating material; and a plurality of word lines formed on the isolation layer inside the trench and covering a sidewall of the active region inside the trench. A separation layer is formed between two neighboring word lines to separate the two neighboring word lines of the plurality of word lines inside the trench with a predetermined distance. The separation layer comprises a second insulating material having an etch selectivity with respect to the first insulating material.
摘要翻译：在一个实施例中，半导体器件包括由形成在具有预定深度的衬底中的沟槽限定的多个鳍状有源区域; 形成在所述沟槽内并包括第一绝缘材料的隔离层; 以及形成在沟槽内的隔离层上并覆盖沟槽内的有源区的侧壁的多个字线。在两个相邻字线之间形成分离层，以将沟槽内的多个字线的两个相邻字线以预定距离分开。分离层包括具有相对于第一绝缘材料的蚀刻选择性的第二绝缘材料。

2. 发明申请

US20070111437A1 SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：包括存储节点的半导体器件及其制造方法
公开(公告)号：US20070111437A1
公开(公告)日：2007-05-17
申请号：US11621507
申请日：2007-01-09
申请人： Chang-Hyun CHO , Tae-Young CHUNG , Cheol-Ju YUN , Jae-Goo LEE , Ju-Yong LEE
发明人： Chang-Hyun CHO , Tae-Young CHUNG , Cheol-Ju YUN , Jae-Goo LEE , Ju-Yong LEE
IPC分类号： H01L21/8242
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L28/91
摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.
摘要翻译：一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

3. 发明申请

US20080266927A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路装置及制造半导体集成电路装置的方法
公开(公告)号：US20080266927A1
公开(公告)日：2008-10-30
申请号：US12055035
申请日：2008-03-25
申请人： Ju-Yong LEE , Sung-Ho JANG , Tae-Young CHUNG , Joon HAN
发明人： Ju-Yong LEE , Sung-Ho JANG , Tae-Young CHUNG , Joon HAN
IPC分类号： G11C5/06 , H01L21/768
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L27/10885 , H01L27/10888 , H01L27/10891 , H01L29/66621
摘要： A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.
摘要翻译：提供了具有6F 2 2布局的半导体集成电路器件。半导体集成电路器件包括衬底; 设置在所述基板中并沿第一方向延伸的多个单位活性区域; 第一和第二存取晶体管，包括设置在衬底上的第一和第二栅极线，并且沿与第一方向成锐角的第二方向延伸跨过单元有源区; 设置在第一和第二栅极线之间的衬底中的第一接合区域和设置在不设置第一接合区域的第一和第二栅极线的侧面上的第二接合区域; 多个位线设置在所述基板上并沿与所述第一方向成锐角的第三方向延伸; 以及直接连接第一连接区域和位线的多个位线触点。

4. 发明申请

US20140103482A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US20140103482A1
公开(公告)日：2014-04-17
申请号：US14109517
申请日：2013-12-17
申请人： Yong-Sung Kim , Tae-Young CHUNG , Soo-Ho SHIN
发明人： Yong-Sung Kim , Tae-Young CHUNG , Soo-Ho SHIN
IPC分类号： H01L29/06 , H01L27/088
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

5. 发明申请

US20070020855A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US20070020855A1
公开(公告)日：2007-01-25
申请号：US11457781
申请日：2006-07-14
申请人： Yong-Sung KIM , Tae-Young CHUNG , Soo-Ho SHIN
发明人： Yong-Sung KIM , Tae-Young CHUNG , Soo-Ho SHIN
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

6. 发明申请

US20090317967A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US20090317967A1
公开(公告)日：2009-12-24
申请号：US12548219
申请日：2009-08-26
申请人： Yong-Sung KIM , Tae-Young CHUNG , Soo-Ho SHIN
发明人： Yong-Sung KIM , Tae-Young CHUNG , Soo-Ho SHIN
IPC分类号： H01L21/28
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件方法。该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。

7. 发明申请

US20070096191A1 COUPLING CAPACITOR AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME 有权
标题翻译：耦合电容器和使用其的半导体存储器件
公开(公告)号：US20070096191A1
公开(公告)日：2007-05-03
申请号：US11461344
申请日：2006-07-31
申请人： Eun-Cheol LEE , Won-Suk YANG , Jin-Woo LEE , Tae-Young CHUNG
发明人： Eun-Cheol LEE , Won-Suk YANG , Jin-Woo LEE , Tae-Young CHUNG
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L28/91 , G11C11/4091
摘要： A coupling capacitor and a semiconductor memory device using the same are provided. In an embodiment, each memory cell of the semiconductor memory device includes a coupling capacitor so that a storage capacitor can store at least 2 bits of data. The coupling capacitor has a capacitance having a predetermined ratio with respect to the capacitance of the storage capacitor. For this, the coupling capacitor is formed by substantially the same fabrication process as the storage capacitor. The predetermined ratio is obtained by choosing an appropriate number of individual capacitors, each with the same capacitance of the storage capacitor, to comprise the coupling capacitor. Also, the coupling capacitor is disposed on an interlayer insulating layer that buries a bit line in a cell region and a sense amplifier in a sense amplifier region.
摘要翻译：提供耦合电容器和使用该耦合电容器的半导体存储器件。在一个实施例中，半导体存储器件的每个存储单元包括耦合电容器，使得存储电容器可以存储至少2位的数据。耦合电容器具有相对于存储电容器的电容具有预定比率的电容。为此，耦合电容器通过与存储电容器基本上相同的制造工艺来形成。通过选择适当数量的各个具有相同电容的存储电容器的单个电容器来获得预定比率，以包括耦合电容器。此外，耦合电容器设置在掩埋单元区域中的位线和读出放大器区域中的读出放大器的层间绝缘层上。

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