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1. 发明申请

US20080266927A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路装置及制造半导体集成电路装置的方法
公开(公告)号：US20080266927A1
公开(公告)日：2008-10-30
申请号：US12055035
申请日：2008-03-25
申请人： Ju-Yong LEE , Sung-Ho JANG , Tae-Young CHUNG , Joon HAN
发明人： Ju-Yong LEE , Sung-Ho JANG , Tae-Young CHUNG , Joon HAN
IPC分类号： G11C5/06 , H01L21/768
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L27/10885 , H01L27/10888 , H01L27/10891 , H01L29/66621
摘要： A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.
摘要翻译：提供了具有6F 2 2布局的半导体集成电路器件。半导体集成电路器件包括衬底; 设置在所述基板中并沿第一方向延伸的多个单位活性区域; 第一和第二存取晶体管，包括设置在衬底上的第一和第二栅极线，并且沿与第一方向成锐角的第二方向延伸跨过单元有源区; 设置在第一和第二栅极线之间的衬底中的第一接合区域和设置在不设置第一接合区域的第一和第二栅极线的侧面上的第二接合区域; 多个位线设置在所述基板上并沿与所述第一方向成锐角的第三方向延伸; 以及直接连接第一连接区域和位线的多个位线触点。

2. 发明申请

US20070111437A1 SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：包括存储节点的半导体器件及其制造方法
公开(公告)号：US20070111437A1
公开(公告)日：2007-05-17
申请号：US11621507
申请日：2007-01-09
申请人： Chang-Hyun CHO , Tae-Young CHUNG , Cheol-Ju YUN , Jae-Goo LEE , Ju-Yong LEE
发明人： Chang-Hyun CHO , Tae-Young CHUNG , Cheol-Ju YUN , Jae-Goo LEE , Ju-Yong LEE
IPC分类号： H01L21/8242
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L28/91
摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.
摘要翻译：一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

3. 发明申请

US20070004129A1 SEMICONDUCTOR DEVICE HAVING FINFET AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有FINFET的半导体器件及其制造方法
公开(公告)号：US20070004129A1
公开(公告)日：2007-01-04
申请号：US11427734
申请日：2006-06-29
申请人： Ju-Yong LEE , Tae-Young CHUNG , Kyu-Hyun LEE , Yong-Sung KIM
发明人： Ju-Yong LEE , Tae-Young CHUNG , Kyu-Hyun LEE , Yong-Sung KIM
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： In one embodiment, a semiconductor device includes a plurality of fin-shaped active regions defined by a trench formed in a substrate with a predetermined depth; an isolation layer formed inside the trench and comprising a first insulating material; and a plurality of word lines formed on the isolation layer inside the trench and covering a sidewall of the active region inside the trench. A separation layer is formed between two neighboring word lines to separate the two neighboring word lines of the plurality of word lines inside the trench with a predetermined distance. The separation layer comprises a second insulating material having an etch selectivity with respect to the first insulating material.
摘要翻译：在一个实施例中，半导体器件包括由形成在具有预定深度的衬底中的沟槽限定的多个鳍状有源区域; 形成在所述沟槽内并包括第一绝缘材料的隔离层; 以及形成在沟槽内的隔离层上并覆盖沟槽内的有源区的侧壁的多个字线。在两个相邻字线之间形成分离层，以将沟槽内的多个字线的两个相邻字线以预定距离分开。分离层包括具有相对于第一绝缘材料的蚀刻选择性的第二绝缘材料。

4. 发明申请

US20060261392A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060261392A1
公开(公告)日：2006-11-23
申请号：US11458353
申请日：2006-07-18
申请人： Ju-Yong LEE , Kyu-Hyun LEE
发明人： Ju-Yong LEE , Kyu-Hyun LEE
IPC分类号： H01L29/94
CPC分类号： H01L27/10855 , H01L21/31144 , H01L21/76831 , H01L21/76897 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.
摘要翻译：本文公开了一种半导体器件及其制造方法，其随着尺寸设计限制的降低而增加这些器件的可靠性。通常，在基板上形成包括导电膜图案和第二绝缘膜图案的第一绝缘膜和布线。在布线的侧壁上形成包括基于氧化硅的材料的第三绝缘膜图案，并且在布线上形成用于限定接触孔区域的侧壁上的接触图形和间隔物。接触孔接触第三绝缘膜图案的表面并穿过第一绝缘膜。因此，可以使布线中使用的第二绝缘膜图案的厚度最小化，从而增加布线之间的间隙填充余量。由于在布线的侧壁上形成具有低介电常数的氧化硅间隔物，所以布线之间的寄生电容可以减小。

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