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1. 发明授权

US07401176B2 Method and system for fast access to stack memory 有权
标题翻译：快速访问堆栈内存的方法和系统
公开(公告)号：US07401176B2
公开(公告)日：2008-07-15
申请号：US10969513
申请日：2004-10-20
申请人： Joshua M. Conner , James H. Grosbach , Joseph W. Triece
发明人： Joshua M. Conner , James H. Grosbach , Joseph W. Triece
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/30134 , G06F9/35 , G06F9/4484
摘要： Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit and the stack pointer, the location of the access RAM can be shifted in order to achieve an index of a literal offset address mode.
摘要翻译：具有堆栈的存储器的快速访问使用地址位，堆栈指针和快速访问随机存取存储器（“RAM”）。当与地址位和堆栈指针一起使用第一地址模式时，可以移位存取RAM的位置，以便实现字面偏移地址模式的索引。

2. 发明授权

US06728856B2 Modified Harvard architecture processor having program memory space mapped to data memory space 有权
标题翻译：改进的哈佛架构处理器具有映射到数据存储空间的程序存储器空间
公开(公告)号：US06728856B2
公开(公告)日：2004-04-27
申请号：US09870648
申请日：2001-06-01
申请人： James H. Grosbach , Joshua M. Conner , Michael Catherwood
发明人： James H. Grosbach , Joshua M. Conner , Michael Catherwood
IPC分类号： G06F1202
CPC分类号： G06F9/3802 , G06F9/342 , G06F9/3824 , G06F12/0223 , G06F12/0623 , G06F15/7857
摘要： A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advantages of simultaneous program instruction and data access, yet provides a means to access program memory resident data without special purpose instructions. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory space. The program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space.
摘要翻译：处理器具有提供哈佛架构的处理速度优势的架构，但是不需要专用指令或两个单独的外部存储器，以便扩展数据存储器和程序指令存储器。处理器具有单独的程序存储器空间和数据存储器空间，但是提供将程序存储空间的至少一部分映射到数据存储空间的能力。这允许被处理的大多数程序指令获得同时的程序指令和数据访问的速度优点，但是提供了访问程序存储器驻留数据而没有专门指令的手段。它还允许程序存储空间和数据存储空间从外部扩展到处理器，只使用一个包含程序指令和数据的外部存储器。处理器包括可操作以存储程序指令和数据的程序存储空间，可操作以存储数据的数据存储空间，以及可操作以将程序存储器空间的至少一部分映射到数据存储空间的映射电路。程序存储空间可能在处理器内部。处理器还可以包括页面寄存器，其可操作以指定映射到数据存储器空间的程序存储器空间的位置。

3. 发明授权

US06985986B2 Variable cycle interrupt disabling 有权
公开(公告)号：US06985986B2
公开(公告)日：2006-01-10
申请号：US09870447
申请日：2001-06-01
申请人： Brian Boles , Joseph W. Triece , Joshua M. Conner
发明人： Brian Boles , Joseph W. Triece , Joshua M. Conner
IPC分类号： G06F13/24 , G06F9/44
CPC分类号： G06F13/24
摘要： A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.

4. 发明授权

US07203818B2 Microcontroller instruction set 有权
标题翻译：微控制器指令集
公开(公告)号：US07203818B2
公开(公告)日：2007-04-10
申请号：US10796771
申请日：2004-03-09
申请人： Edward Brian Boles , Rodney Jay Drake , Darrel Ray Johansen , Sumit K. Mitra , Randy Yach , James Grosbach , Joshua M. Conner , Joseph W. Triece
发明人： Edward Brian Boles , Rodney Jay Drake , Darrel Ray Johansen , Sumit K. Mitra , Randy Yach , James Grosbach , Joshua M. Conner , Joseph W. Triece
IPC分类号： G06F12/00 , G06F15/00
CPC分类号： G06F9/30192 , G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/321 , G06F9/325
摘要： A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.
摘要翻译：微控制器装置设置有用于操纵微控制器的行为的指令集。提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。可以通过寄存器文件或数据存储器进行直接或间接寻址。特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。因此，两个文件寄存器用于一些两个操作数指令。这允许在两个寄存器之间直接移动数据，而不经过W寄存器。因此，提高性能并减少程序内存使用。

5. 发明授权

US06601160B2 Dynamically reconfigurable data space 有权
标题翻译：动态可重构数据空间
公开(公告)号：US06601160B2
公开(公告)日：2003-07-29
申请号：US09870448
申请日：2001-06-01
申请人： Michael Catherwood , Joseph W. Triece , Michael Pyska , Joshua M. Conner
发明人： Michael Catherwood , Joseph W. Triece , Michael Pyska , Joshua M. Conner
IPC分类号： G06F1576
CPC分类号： G06F9/342 , G06F9/30185 , G06F9/345 , G06F12/0284 , G06F12/109
摘要： A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.
摘要翻译：提供了一种处理器，其具有数据存储器，该数据存储器可以以一种模式被寻址为双存储器空间，并且在另一种模式下可以被寻址为单个线性存储器空当处理DSP指令时，存储器可能允许从数据存储器获取双重并发操作数。然后，存储器可以动态地允许相同的存储器作为用于非DSP指令的单个线性存储器地址空间被访问。

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