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1. 发明申请

US20120181508A1 Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits 有权
标题翻译：三维混合集成电路中的石墨烯器件和硅场效应晶体管
公开(公告)号：US20120181508A1
公开(公告)日：2012-07-19
申请号：US13009280
申请日：2011-01-19
申请人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
发明人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0688 , H01L21/28506 , H01L21/8221 , H01L29/1606 , H01L29/66045 , H01L29/78 , H01L29/78684
摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.
摘要翻译：三维集成电路包括硅衬底，设置在衬底上的第一源极区域，设置在衬底上的第一漏极区域，设置在衬底上的第一栅极堆叠部分，设置在第一源极区域上的第一电介质层，第一漏极区域，第一栅极堆叠部分和衬底，形成在第一电介质层上的第二电介质层，设置在第二电介质层上的第二源极区域，设置在第二电介质层上的第二漏极区域，以及第二漏极区域栅极堆叠部分设置在第二介电层上，第二栅极堆叠部分包括石墨烯层。

2. 发明授权

US08409957B2 Graphene devices and silicon field effect transistors in 3D hybrid integrated circuits 有权
公开(公告)号：US08409957B2
公开(公告)日：2013-04-02
申请号：US13009280
申请日：2011-01-19
申请人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
发明人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
IPC分类号： H01L21/336
CPC分类号： H01L27/0688 , H01L21/28506 , H01L21/8221 , H01L29/1606 , H01L29/66045 , H01L29/78 , H01L29/78684
摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

3. 发明授权

US08748871B2 Graphene devices and semiconductor field effect transistors in 3D hybrid integrated circuits 有权
标题翻译：石墨烯装置和3D混合集成电路中的半导体场效应晶体管
公开(公告)号：US08748871B2
公开(公告)日：2014-06-10
申请号：US13352737
申请日：2012-01-18
申请人： Phaedon Avouris , Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu , Yanqing Wu , Wenjuan Zhu
发明人： Phaedon Avouris , Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L27/088
CPC分类号： H01L27/0688 , B82Y10/00 , H01L29/1606 , H01L29/78684
摘要： A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.
摘要翻译：三维集成电路包括半导体器件，形成在半导体器件上的绝缘体，形成在绝缘体中的互连以及形成在绝缘体上的石墨烯器件。

4. 发明授权

US08587067B2 Graphene devices and silicon field effect transistors in 3D hybrid integrated circuits 有权
标题翻译：三维混合集成电路中的石墨烯器件和硅场效应晶体管
公开(公告)号：US08587067B2
公开(公告)日：2013-11-19
申请号：US13559941
申请日：2012-07-27
申请人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
发明人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
IPC分类号： H01L27/088
CPC分类号： H01L27/0688 , H01L21/28506 , H01L21/8221 , H01L29/1606 , H01L29/66045 , H01L29/78 , H01L29/78684
摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.
摘要翻译：三维集成电路包括硅衬底，设置在衬底上的第一源极区域，设置在衬底上的第一漏极区域，设置在衬底上的第一栅极堆叠部分，设置在第一源极区域上的第一电介质层，第一漏极区域，第一栅极堆叠部分和衬底，形成在第一电介质层上的第二电介质层，设置在第二电介质层上的第二源极区域，设置在第二电介质层上的第二漏极区域，以及第二漏极区域栅极堆叠部分设置在第二介电层上，第二栅极堆叠部分包括石墨烯层。

5. 发明申请

US20120292702A1 Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits 有权
公开(公告)号：US20120292702A1
公开(公告)日：2012-11-22
申请号：US13559941
申请日：2012-07-27
申请人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
发明人： Josephine B. Chang , Wilfried E. Haensch , Fei Liu , Zihong Liu
IPC分类号： H01L27/088 , B82Y99/00
CPC分类号： H01L27/0688 , H01L21/28506 , H01L21/8221 , H01L29/1606 , H01L29/66045 , H01L29/78 , H01L29/78684
摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

6. 发明授权

US09368502B2 Replacement gate multigate transistor for embedded DRAM 有权
标题翻译：用于嵌入式DRAM的替换门多栅极晶体管
公开(公告)号：US09368502B2
公开(公告)日：2016-06-14
申请号：US13274758
申请日：2011-10-17
申请人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
发明人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
IPC分类号： H01L27/108 , H01L21/02 , H01L21/84 , H01L29/78 , H01L29/49 , H01L29/66
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译：存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。

7. 发明申请

US20130092992A1 REPLACEMENT GATE MULTIGATE TRANSISTOR FOR EMBEDDED DRAM 有权
标题翻译：嵌入式DRAM的更换栅极多晶硅晶体管
公开(公告)号：US20130092992A1
公开(公告)日：2013-04-18
申请号：US13274758
申请日：2011-10-17
申请人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
发明人： Josephine B. Chang , Leland Chang , Michael A. Guillorn , Wilfried E. Haensch
IPC分类号： H01L27/108 , H01L21/02 , B82Y99/00
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译：存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。

8. 发明申请

US20120038429A1 Oscillator Circuits Including Graphene FET 审中-公开
标题翻译：包括石墨烯FET的振荡器电路
公开(公告)号：US20120038429A1
公开(公告)日：2012-02-16
申请号：US12856269
申请日：2010-08-13
申请人： Wilfried E. Haensch , Yong Liu , Zihong Liu
发明人： Wilfried E. Haensch , Yong Liu , Zihong Liu
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1203 , H03B5/1215 , H03B2200/0008
摘要： An oscillator circuit includes a field effect transistor (FET), the FET comprising a channel, source, drain, and gate, wherein at least the channel comprises graphene; an LC component connected to the FET, the LC component comprising at least one inductor and at least one capacitor; and a feedback loop connecting the FET source to the FET drain via the LC component.
摘要翻译：振荡器电路包括场效应晶体管（FET），所述FET包括沟道，源极，漏极和栅极，其中至少所述沟道包括石墨烯; 连接到所述FET的LC部件，所述LC部件包括至少一个电感器和至少一个电容器; 以及通过LC部件将FET源连接到FET漏极的反馈环路。

9. 发明授权

US08860107B2 FinFET-compatible metal-insulator-metal capacitor 有权
标题翻译： FinFET兼容金属 - 绝缘体 - 金属电容器
公开(公告)号：US08860107B2
公开(公告)日：2014-10-14
申请号：US12793292
申请日：2010-06-03
申请人： Wilfried E. Haensch , Pranita Kulkarni , Tenko Yamashita
发明人： Wilfried E. Haensch , Pranita Kulkarni , Tenko Yamashita
IPC分类号： H01L27/108 , H01L21/8234 , H01L27/08 , H01L27/06
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0805
摘要： At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer.
摘要翻译：用于电容器的至少一个半导体鳍片与用于场效应晶体管的其它半导体鳍片同时形成。沉积下导电层并以光刻方式图案化以形成位于至少一个半导体鳍片上的下导电板。形成电介质层和至少一个上导电层，并将其光刻图案化以在下导电板上形成节点电介质和上导电板，以及在其它半导体鳍片上的栅极电介质和栅极导体。下导电板，节点电介质和上导电板共同形成电容器。 finFET可以是双栅极finFET或者触发的finFET。埋入的绝缘体层可以任选地凹入以增加电容。或者，下导电板可以形成在掩埋绝缘体层的平坦表面上。

10. 发明授权

US08492794B2 Vertical polysilicon-germanium heterojunction bipolar transistor 有权
公开(公告)号：US08492794B2
公开(公告)日：2013-07-23
申请号：US13048366
申请日：2011-03-15
申请人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L29/66
CPC分类号： H01L29/737 , H01L21/76229 , H01L29/0649 , H01L29/0821 , H01L29/165 , H01L29/66242 , H01L29/7375
摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

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