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1. 发明授权

US4338138A Process for fabricating a bipolar transistor 失效
标题翻译：制造双极晶体管的工艺
公开(公告)号：US4338138A
公开(公告)日：1982-07-06
申请号：US126611
申请日：1980-03-03
申请人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
发明人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/285 , H01L21/331 , H01L21/762 , H01L27/06 , H01L29/73 , H01L29/732 , H01L21/263 , H01L21/203 , H01L21/22 , H01L21/31
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/28525 , H01L21/76229 , H01L21/76232 , H01L29/7325 , Y10S148/131
摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.
摘要翻译：一种改进的双极晶体管结构，其形成在第一导电类型的硅衬底的平坦表面上的薄外延层的非常小的区域中，所述薄外延层的非常小的面积具有延伸到所述衬底的平坦表面的垂直侧壁，所述薄外延层的区域包含按顺序列出的具有暴露平面的第二导电类型的浅深度发射极区域，所述第一导电类型的浅深度基底区域和所述第二导电类型的浅深度有源集电极区域围绕所述发射极，基极和主动集电极区域的所述第一导电类型的细长区域，所述细长区域包含在所述薄外延层的所述小区域的所述垂直侧壁内并与之共同延伸，由此基极集电极电容由于到基极 - 集电极结的非常小的区域。还公开了用于制造改进的双极晶体管结构的工艺和替代工艺。

2. 发明授权

UST106101I4 Structure of an improved bipolar transistor 失效
标题翻译：改进的双极晶体管的结构
公开(公告)号：UST106101I4
公开(公告)日：1985-12-03
申请号：US695657
申请日：1985-01-28
申请人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
发明人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
IPC分类号： H01L21/285 , H01L21/331 , H01L21/762 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/28525 , H01L21/76229 , H01L21/76232 , H01L29/7325
摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layer containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction.

3. 发明授权

US4378630A Process for fabricating a high performance PNP and NPN structure 失效
标题翻译：制造高性能PNP和NPN结构的工艺
公开(公告)号：US4378630A
公开(公告)日：1983-04-05
申请号：US309627
申请日：1981-10-08
申请人： Cheng T. Horng , Richard R. Konian , Robert O. Schwenker , Armin W. Weider
发明人： Cheng T. Horng , Richard R. Konian , Robert O. Schwenker , Armin W. Weider
IPC分类号： H01L21/331 , H01L21/762 , H01L21/8224 , H01L27/082 , H01L29/10 , H01L29/423 , H01L21/203 , H01L21/22
CPC分类号： H01L29/66272 , H01L21/76202 , H01L21/76229 , H01L21/76232 , H01L21/8224 , H01L27/0821 , H01L29/1004 , H01L29/42304
摘要： Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.
摘要翻译：公开了具有非常高的速度和低功率要求的PNP和NPN类型的非常小的集成电路器件的制造和结构。该结构提供了在同一半导体芯片内形成的垂直NPN和横向PNP晶体管。横向PNP晶体管的基极宽度非常窄（约300至400纳米）。这个窄尺寸部分通过使用明确定义的化学气相沉积（CVD）氧化物掩模而不是常规的光刻掩模来获得。为了消除注入衬底的发射极电流，PNP晶体管的P +发射极和P +集电极由氮化硅和二氧化硅介电层界定。

4. 发明授权

US4339767A High performance PNP and NPN transistor structure 失效
标题翻译：高性能PNP和NPN晶体管结构
公开(公告)号：US4339767A
公开(公告)日：1982-07-13
申请号：US146921
申请日：1980-05-05
申请人： Cheng T. Horng , Richard R. Konian , Robert O. Schwenker , Armin W. Wieder
发明人： Cheng T. Horng , Richard R. Konian , Robert O. Schwenker , Armin W. Wieder
IPC分类号： H01L21/331 , H01L21/762 , H01L21/8224 , H01L21/8228 , H01L27/082 , H01L29/10 , H01L29/423 , H01L29/73 , H01L29/732 , H01L29/735 , H01L27/02 , H01L29/04
CPC分类号： H01L29/66272 , H01L21/76202 , H01L21/76229 , H01L21/76232 , H01L21/8224 , H01L27/0821 , H01L29/1004 , H01L29/42304 , H01L29/7325 , H01L29/735
摘要： Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.
摘要翻译：公开了具有非常高的速度和低功率要求的PNP和NPN类型的非常小的集成电路器件的制造和结构。该结构提供了在同一半导体芯片内形成的垂直NPN和横向PNP晶体管。横向PNP晶体管的基极宽度非常窄（约300至400纳米）。这个窄尺寸部分通过使用明确定义的化学气相沉积（CVD）氧化物掩模而不是常规的光刻掩模来获得。为了消除注入衬底的发射极电流，PNP晶体管的P +发射极和P +集电极由氮化硅和二氧化硅介电层界定。

5. 发明授权

US4308469A Unity gain emitter follower bridge circuit 失效
标题翻译：单位增益射极跟随器桥接电路
公开(公告)号：US4308469A
公开(公告)日：1981-12-29
申请号：US97013
申请日：1979-11-23
申请人： Joseph R. Cavaliere , Robert A. Henle , Richard R. Konian , James L. Walsh
发明人： Joseph R. Cavaliere , Robert A. Henle , Richard R. Konian , James L. Walsh
IPC分类号： H03K19/082 , H03K19/086 , H03K19/013 , H03K19/20
CPC分类号： H03K19/082 , H03K19/0826
摘要： A high speed, unity gain, emitter follower OR circuit is disclosed including first and second pairs of emitter-connected complementary bipolar transistors with the bases of the NPN transistors being connected together and the bases of the PNP transistors being connected commonly to an input line. One of the NPN transistors id diode-connected (base to collector). The emitter of the other NPN transistor is connected to an output terminal. The input line is connected to the emitters of a pair of OR input NPN transistors and to a first current source. A second current source is coupled to the diode-connected NPN transistor.
摘要翻译：公开了一种高速，单位增益，射极跟随器或电路，包括第一和第二对发射极连接的互补双极晶体管，其中NPN晶体管的基极连接在一起，并且PNP晶体管的基极共同连接到输入线。其中一个NPN晶体管是二极管连接的（基极到集电极）。另一个NPN晶体管的发射极连接到输出端。输入线连接到一对OR输入NPN晶体管的发射极和第一电流源。第二电流源耦合到二极管连接的NPN晶体管。

6. 发明授权

US4287435A Complementary transistor inverting emitter follower circuit 失效
标题翻译：互补晶体管反相发射极跟随器电路
公开(公告)号：US4287435A
公开(公告)日：1981-09-01
申请号：US082254
申请日：1979-10-05
申请人： Joseph R. Cavaliere , Robert A. Henle , Richard R. Konian , James L. Walsh
发明人： Joseph R. Cavaliere , Robert A. Henle , Richard R. Konian , James L. Walsh
IPC分类号： H03K19/086 , H03K5/02 , H03K17/04 , H03K17/60 , H03K17/66 , H03K19/082 , H03K3/26
CPC分类号： H03K19/082 , H03K5/02
摘要： A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the V.sub.be necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other.In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal. In a logic circuit species of the invention, the emitter of one of the second pair of transistors is connected to the base of the other of the second pair of transistors. NOR logic is performed by connecting additional transistors in parallel with said one of the second pair of transistors, the bases of the additional transistors receiving respective logic input signals. The output from the driver circuit as well as from the logic circuit is derived from the commonly connected emitters of the first pair of transistors. The first pair of transistors conduct only during the transitions of the input signals.
摘要翻译：一种互补双极晶体管电路，其特征在于输入和输出电压转换的输出阻抗相同，输入和输出之间的输入和输出之间只有一个收集器路径延迟，用于输入电压转换和非常低的待机功耗。提供了同时使具有电压摆幅的信号同时致动串联连接的发射极跟随器的第一对互补晶体管，该电压摆幅仅为第一对晶体管的每个基极 - 发射极二极管正向偏置所需的Vbe的一部分。使用第二对互补晶体管实现激活，其具有连接到第一对类似晶体管的相应基极的集电极。第二对晶体管中的每一个的剩余电极中的一个彼此连接。在本发明的驱动电路种类中，第二对晶体管的基极相互连接并接收输入信号。在本发明的逻辑电路种类中，第二对晶体管之一的发射极连接到第二对晶体管的另一对的基极。通过将另外的晶体管与所述第二对晶体管中的所述一个并联连接来执行NOR逻辑，所述附加晶体管的基极接收相应的逻辑输入信号。来自驱动器电路以及来自逻辑电路的输出源自第一对晶体管的共同连接的发射极。第一对晶体管仅在输入信号的转变期间导通。

7. 发明授权

US4252581A Selective epitaxy method for making filamentary pedestal transistor 失效
标题翻译：用于制作丝状基座晶体管的选择性外延法
公开(公告)号：US4252581A
公开(公告)日：1981-02-24
申请号：US080648
申请日：1979-10-01
申请人： Narasipur G. Anantha , Joseph R. Cavaliere , Richard R. Konian , Gurumakonda R. Srinivasan , Herbert I. Stoller , James L. Walsh
发明人： Narasipur G. Anantha , Joseph R. Cavaliere , Richard R. Konian , Gurumakonda R. Srinivasan , Herbert I. Stoller , James L. Walsh
IPC分类号： H01L21/033 , H01L29/08 , H01L29/10 , H01L21/20 , H01L21/302
CPC分类号： H01L21/033 , H01L29/0826 , H01L29/1004 , Y10S148/131 , Y10S148/141
摘要： A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.
摘要翻译：一种用于制造由于消除外部基极 - 集电极结而引起的基极集电极电容降低的双极丝基座晶体管的方法。硅沉积在共面氧化物 - 硅表面上，其中只有掩埋式集电极基座的顶部硅表面通过氧化物暴露。外延硅沉积在暴露的基座表面上，而多晶硅沉积在氧化物表面上。除了在基底区域之外，多晶硅被蚀刻掉。在基极区域形成发射极，并将触点制成发射极，基极和集电极区域。

8. 发明授权

US4458159A Large swing driver/receiver circuit 失效
标题翻译：大摆动驱动器/接收器电路
公开(公告)号：US4458159A
公开(公告)日：1984-07-03
申请号：US392189
申请日：1982-06-25
申请人： Richard R. Konian
发明人： Richard R. Konian
IPC分类号： H03K19/086 , H03K5/02 , H03K19/013 , H03K19/018 , H03K19/082 , H03K3/01
CPC分类号： H03K5/02 , H03K19/013 , H03K19/01825 , H03K19/082
摘要： Low voltage, low power transistor driver/receiver and logic circuits are disclosed comprising a pair of NPN transistors, the base of the first transistor being directly connected to an input terminal and, via a resistor, to the base of the second transistor. A third NPN transistor is connected with the second transistor in series circuit across a low voltage power supply. The junction between the series-connected transistors is coupled to an output terminal. A diode is connected between a point on the resistor and the collector of the second transistor to prevent saturation. The emitter of the second transistor is connected through a small or zero resistance to one terminal of the power supply. The down level at the output terminal is held by a transistor or diode clamp connected between the base of the third transistor and the other terminal of the power supply.Various embodiments of the circuits are disclosed to provide driver and logic functions and to permit tailoring of the circuits to various load conditions requiring different output signal swing amplitudes and different response times.
摘要翻译：公开了低压，低功率晶体管驱动器/接收器和逻辑电路，其包括一对NPN晶体管，第一晶体管的基极直接连接到输入端子，并且经由电阻器连接到第二晶体管的基极。第三NPN晶体管通过低压电源与串联电路中的第二晶体管连接。串联晶体管之间的结连接到输出端。二极管连接在电阻上的点和第二晶体管的集电极之间，以防止饱和。第二晶体管的发射极通过小电阻或零电阻连接到电源的一个端子。输出端子的下降电平由连接在第三晶体管的基极和电源的另一个端子之间的晶体管或二极管钳位保持。公开了电路的各种实施例以提供驱动器和逻辑功能，并且允许将电路定制到需要不同输出信号摆幅幅度和不同响应时间的各种负载条件。

9. 发明授权

US5362986A Vertical chip mount memory package with packaging substrate and memory chip pairs 失效
标题翻译：垂直芯片安装存储器封装，封装衬底和存储器芯片对
公开(公告)号：US5362986A
公开(公告)日：1994-11-08
申请号：US109230
申请日：1993-08-19
申请人： John M. Angiulli , Eugene S. Kolankowsky , Richard R. Konian , Leon L. Wu
发明人： John M. Angiulli , Eugene S. Kolankowsky , Richard R. Konian , Leon L. Wu
IPC分类号： H01L23/12 , H01L25/00 , H01L25/065 , H01L25/18 , H01L27/10 , H01L23/498 , H01L23/538
CPC分类号： H01L25/18 , H01L25/0652 , H01L2924/0002 , Y10T29/49144
摘要： A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19)mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form the memory chip cube. One is a high melting point lead tin alloy (HMA), another is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over other functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs.
摘要翻译：封装基板（10）上安装有安装在基板上的存储芯片立方体（40）和水平安装的互连芯片（19），其在组装期间使用两种铅锡焊料合金接合以形成存储器芯片立方体。一种是高熔点铅锡合金（HMA），另一种是低熔点铅锡合金（LMA）。存储器立方体的存储器芯片组（11）通过在切割之前将功能存储器芯片放置在其它功能存储器芯片上而形成。单个存储器芯片的芯片焊盘和晶片内的存储器芯片的引线锡焊盘对准，并且高熔点铅锡焊料回流，形成存储器芯片对。

10. 发明授权

US5397747A Vertical chip mount memory package and method 失效
标题翻译：垂直芯片安装存储器封装和方法
公开(公告)号：US5397747A
公开(公告)日：1995-03-14
申请号：US151455
申请日：1993-11-02
申请人： John M. Angiulli , Eugene S. Kolankowsky , Richard R. Konian , Leon L. Wu
发明人： John M. Angiulli , Eugene S. Kolankowsky , Richard R. Konian , Leon L. Wu
IPC分类号： H01L23/12 , H01L25/00 , H01L25/065 , H01L25/18 , H01L27/10 , H01L21/60
CPC分类号： H01L25/18 , H01L25/0652 , H01L2924/0002 , Y10T29/49144
摘要： A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19) mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form memory chip cube. One is a high melting point lead tin alloy (HMA), the other is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over another functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs. The memory cube (42) is formed by joining the memory chip pairs together in a boat (30) with a silicon bar (41) maintaining spacing during manufacture. The memory chip cube (42) as well as the supporting chips are then placed and joined to the packaging substrate. The supporting silicon bar is removed from the memory chip cube (42) by re-heating the cube after it is joined to the packaging substrate. The package is completed by following with capping of the chip package of the paired memory chip cube with its attached packaging substrate by attaching to the base member substrate an appropriate heat sink after appropriate I/O flex lines are in place.
摘要翻译：封装基板（10）上安装有安装在基板上的存储芯片立方体（40）和水平安装的互连芯片（19），其在组装期间使用两种铅锡焊料合金接合以形成存储芯片立方体。一种是高熔点铅锡合金（HMA），另一种是低熔点铅锡合金（LMA）。存储器立方体的存储器芯片对（11）通过在功能存储器芯片被切割之前将功能存储器芯片放置在另一个功能存储器芯片上而形成。单个存储器芯片的芯片焊盘和晶片内的存储器芯片的引线锡焊盘对准，并且高熔点铅锡焊料回流，形成存储器芯片对。存储器立方体（42）通过在存储器芯片对中将存储芯片组合在一起而形成，所述存储器芯片对在制造期间保持间隔的硅棒（41）在舟皿（30）中。然后将存储芯片立方体（42）以及支撑芯片放置并连接到封装基板。立方体在与包装基板接合后再加热立方体，从存储芯片立方体（42）移除支撑硅棒。通过在配对的存储芯片立方体的芯片封装与其附接的封装基板之间通过在适当的I / O柔性线就位之后附接到基底构件基板上的合适的散热器来完成封装。

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